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Displaying 1 - 4 of 4 documents.

Title	Document #	Date
A PROCEDURE FOR MEASURING P-CHANNEL MOSFET HOT-CARRIER-INDUCED DEGRADATION AT MAXIMUM GATE CURRENT UNDER DC STRESS:	JESD60A	Sep 2004
This method establishes a standard procedure for accelerated testing of the hot-carrier-induced change of a p-channel MOSFET. The objective is to provide a minimum set of measurements so that accurate comparisons can be made between different technologies. The measurements specified should be viewed as a starting pint in the characterization and benchmarking of the trasistor manufacturing process. Committee(s): JC-14.2 Free download. Registration or login required.
Reinstated.	TO-059	Jan 2003
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Plastic Multi Position Flange Mount Mixed Technology, 0.10 in. Pitch Package	TO-220L.01	Nov 2020
Item 11.10-456(E) Committee(s): JC-11, JC-11.10 JEP95 Registrations Main Page Free download. Registration or login required.
THERMAL IMPEDANCE MEASUREMENT FOR INSULATED GATE BIPOLAR TRANSISTORS - (Delta VCE(on) Method)	JESD24-12	Jun 2004
The purpose of this test method is to measure the thermal impedance of the IGBT (Insulated Gate Bipolar Transistor) under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity of the collector-emitter on voltage, VCE(on), is used as the junction temperature indicator. This is an alternative method to JEDEC Standard No. 24-6. Committee(s): JC-25 Free download. Registration or login required.