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Title	Document #	Date
HIGH TEMPERATURE STORAGE LIFE	JESD22-A103E.01	Jul 2021
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). Thermally activated failure mechanisms are modeled using the Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used without electrical conditions applied. This test may be destructive, depending on time, temperature and packaging (if any). Committee(s): JC-14.1 Available for purchase: $55.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
LOW TEMPERATURE STORAGE LIFE Status: Reaffirmed May 2021	JESD22-A119A	Oct 2015
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices Low Temperature storage test is typically used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). During the test reduced temperatures (test conditions) are used without electrical stress applied. This test may be destructive, depending on Time, Temperature and Packaging (if any). Committee(s): JC-14.1 Free download. Registration or login required.