Standards & Documents Search

Displaying 1 - 8 of 8 documents. Show 5 results per page.

Title	Document #	Date
144 Pin DDR SGRAM SO-DIMM	MODULE4.5.9	Mar 1999
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
GDDR2 Specific SGRAM Functions	SDRAM3.11.5.6	May 2005
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
GDDR3 Specific SGRAM Functions	SDRAM3.11.5.7	May 2005
Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
POD18 - 1.8 V PSEUDO OPEN DRAIN I/O	JESD8-19	Dec 2006
This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.8 V Pseudo Open Drain I/Os. The 1.8 V Pseudo Open Drain interface, also known as POD18, is primarily used to communicate with GDDR3 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required.
POD15 - 1.5 V PSEUDO OPEN DRAIN I/O	JESD8-20A	Oct 2009
This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily used to communicate with GDDR4 and GDDR5 SGRAM devices. Item 135.01 Committee(s): JC-16 Free download. Registration or login required.
Graphics Double Data (GDDR4) SGRAM Standard	SDRAM3.11.5.8	May 2006
Release No. 16. Item 1600.41, 1656.0 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
POD135 - 1.35 V PSEUDO OPEN DRAIN I/O	JESD8-21C	Jun 2019
This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance's, and the termination and calibration scheme for 1.35 V Pseudo Open Drain I/Os. The 1.35 V Pseudo Open Drain interface, also known as POD135, is primarily used to communicate with GDDR5 or GDDR5M SGRAM devices. Item 146.01B Committee(s): JC-16 Free download. Registration or login required.
GRAPHICS DOUBLE DATA RATE (GDDR5) SGRAM STANDARD	JESD212C	Feb 2016
This document defines the Graphics Double Data Rate 5 (GDDR5) Synchronous Graphics Random Access Memory (SGRAM), including features, functionality, package, and pin assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC standard compatible 512 Mb through 8 Gb x32 GDDR5 SGRAM devices. System designs based on the required aspects of this standard will be supported by all GDDR5 SGRAM vendors providing JEDEC standard compatible devices. Some aspects of the GDDR5 standard such as AC timings and capacitance values were not standardized. Some features are optional and therefore may vary among vendors. In all cases, vendor data sheets should be consulted for specifics. Item 1733.70B Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3C Free download. Registration or login required.