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Title	Document #	Date
1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE	JESD8-26	Sep 2011
This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.2 V and is primarily intended to support communications with Wide I/O SDRAM devices. Committee(s): JC-16 Free download. Registration or login required.
100 Pin DRAM, SDRAM, and ROM DIMM	MODULE4.4.8	Dec 1997
Release No. 8 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification	MODULE4.20.9	Nov 2004
Release No. 14 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin and 168 Pin PEMM Families with EDO-DRAM and SDRAM	MODULE4.5.13	Oct 2000
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin SDRAM SO-DIMM	MODULE4.5.6	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

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