Standards & Documents Search

Release No. 8

Committee(s): JC-42.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 10

Committee(s): JC-42

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 16

Committee(s): JC-45, JC-45.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No.31

This revision contains terminology updates only.

Committee(s): JC-42, JC-42.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 31

This revision contains terminology updates only.

Committee(s): JC-42, JC-42.5

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 13

Committee(s): JC-42.5

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 24;

Item 2114.44

Committee(s): JC-45, JC-45.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 14

Committee(s): JC-45.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 19A.  Items 2133.37, 2191.00, 2191.02, 2129.12, 2113.33.

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 31. Item 2131.03, 2078.04, 2131.06

This revision contains terminology updates only.

Committee(s): JC-45, JC-45.2, JC-45.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

This document defines the Low Power Double Data Rate (LPDDR) SDRAM 1.2 V I/O, including AC and DC operating conditions, extended mode register settings, and I-V characteristics. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 2 Gb for x16 and x32 Low Power Double Data Rate SDRAM devices with 1.2 V I/O. System designs based on the required aspects of this specification will be supported by all LPDDR SDRAM vendors providing compliant devices.

Committee(s): JC-42.6

Free download. Registration or login required.

Release No. 21
Item 2202.01

Committee(s): JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Committee Document Reference Title: LPDDR3 and LPDDR4 SPD Document Release 1
Device Type Identifier: LP-DIMM Revision 1.0

This Annex describes the serial presence detect (SPD) values for all LPDDR modules. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. The following SPD fields will be documented in the order presented in Section 2, with the exception of bytes 128~255 which are documented in separate sections, one for each family of module types. Further description of Byte 2 is found in Annex A of the SPD standard. Item 2254.01

Committee(s): JC-45

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No. 19

Committee(s): JC-45, JC-45.1

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

Release No.13

Committee(s): JC-42, JC-42.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.

This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01

Committee(s): JC-42, JC-42.3

Free download. Registration or login required.

This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-42.3

Available for purchase: $247.00 Add to Cart

Paying JEDEC Members may login for free access.

This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR SDRAM vendors providing JEDEC compliant devices.

Committee(s): JC-42.3

Free download. Registration or login required.

Release No. 9

Committee(s): JC-42.3

JESD21-C Solid State Memory Documents Main Page

Free download. Registration or login required.