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Title	Document #	Date
100 Pin DRAM, SDRAM, and ROM DIMM	MODULE4.4.8	Dec 1997
Release No. 8 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin SDRAM SO-DIMM	MODULE4.5.6	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
VCSDRAM Specific SDRAM Functions	SDRAM3.11.5.4	Jun 1999
Release No. 9 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Enhanced SDRAM (ESDRAM) Specific SDRAM Functions	SDRAM3.11.5.3	Jun 1999
Release No. 9 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin and 168 Pin PEMM Families with EDO-DRAM and SDRAM	MODULE4.5.13	Oct 2000
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
200 Pin SDRAM DIMM	MODULE4.5.2	Oct 2001
Release No.11 Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin Registered SDRAM DIMM Family	MODULE4.5.7	Oct 2001
Release No.11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
General SDRAM Functions	SDRAM3.11.5.1	Jun 2002
Release No. 12 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR Specific SDRAM Functions	SDRAM3.11.5.2	Jun 2003
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - 240 pin DDR2 SDRAM, 1.00 mm contact centers, Socket Outline. Item 11.14-061.	SO-001B	Jul 2003
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
200 Pin, PC-2700/PC-2100/PC-1600 Unbuffered SO-DIMM SDRAM Reference Design Specification	MODULE4.20.6	Oct 2003
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Nibble Wide SDRAM	SDRAM3.11.2	Jan 2004
Release No.13 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide SDRAM	SDRAM3.11.3	Jan 2004
Release No.13 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex D, DDR Synchronous DRAM (DDR SDRAM)	SPD4.1.2.4	Jan 2004
Release No.13 Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
214-Pin DDR2 SDRAM Unbuffered MicroDIMM Design Specification	MODULE4.20.12	Apr 2004
Release No. 14 Committee(s): JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification	MODULE4.20.9	Nov 2004
Release No. 14 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS	JESD8-17	Nov 2004
This material is intended to be reflected in supplier specifications for point to point DDR devices ranging from 400 Mb/s to 800 Mb/s operation. It is a method to specify driver impedance with something other than a number that does not nec-essarily define how it operates in a real net This standard addresses this issue using net lengths and specifies how much uncertainty can exist in the data for each speed supported. Committee(s): JC-16.1, JC-16 Free download. Registration or login required.
SDRAM and SGRAM Architectural Operational Features Table of Contents	SDRAM3.11.5.TOC	May 2006
Release No.16 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
SPD Annex I, Serial Presence Detect for Virtual Channel SDRAM, Revision 2	SPD4.1.2.9	Jun 2006
Release No.9A Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - DDR2 SDRAM DIMM (Dual Inline memory Module) Family, Flex-Based, 1.00 mm Contact Centers.	MO-281-A	Nov 2006
Item 11.14-100 Patents(): STAKTEK: See Outline Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
SPD Annex J: Serial Presence Detect for DDR2 SDRAM	SPD4.1.2.10	Jan 2007
Release No. 17 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144-Pin EP2-2100 DDR2 SDRAM 32b S0DIMM Design Specification, Rev 1.0. Item 2043.09.	MODULE4.20.16	Feb 2007
Release No. 16 Committee(s): JC-45, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - 204 Pin SO-DDR3 SDRAM, 0.60 mm Contact Centers, Socket Outline.	SO-006B	Oct 2007
Item 11.14-114 Patents(): Foxconn (Hon Hai): 5,882,211, 6,113,398 Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR3 SDRAM DIMM (Dual Inline Memory Module) Family, Flex-Based, 1.00 mm contact Centers	MO-290-A	Nov 2007
Item 11.14-118 Patents(): STAKTEK, See Outline Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
SPECIALITY DDR2-1066 SDRAM	JESD208	Nov 2007
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. Committee(s): JC-42.3 Free download. Registration or login required.
DOUBLE DATA RATE (DDR) SDRAM STANDARD	JESD79F	Feb 2008
This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR SDRAM vendors providing JEDEC compliant devices. Committee(s): JC-42.3 Free download. Registration or login required.
Word Wide SDRAM.	SDRAM3.11.4	Feb 2008
Release No. 17. Item 1749.01 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
200-Pin DDR2 SDRAM Unbuffered SODIMM Design Specification	MODULE4.20.11	Jun 2008
Release No. 18. Item 2168.01 Committee(s): JC-45, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR2 Specific SDRAM Function	SDRAM3.11.5.5	Jul 2008
Release No. 18 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O.	JESD209A-1	Mar 2009
This document defines the Low Power Double Data Rate (LPDDR) SDRAM 1.2 V I/O, including AC and DC operating conditions, extended mode register settings, and I-V characteristics. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 2 Gb for x16 and x32 Low Power Double Data Rate SDRAM devices with 1.2 V I/O. System designs based on the required aspects of this specification will be supported by all LPDDR SDRAM vendors providing compliant devices. Committee(s): JC-42.6 Free download. Registration or login required.
Annex W, R/C W, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.07	MODULE4.20.20.W	Aug 2009
Release No. 19 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex Y, R/C Y, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.06	MODULE4.20.20.Y	Aug 2009
Release No. 19 Committee(s): JC-45.1, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR2 SDRAM STANDARD	JESD79-2F	Nov 2009
This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01 Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
240-Pin PC2-6400/PC2-5300/PC2-4200/PC2-3200 DDR2 SDRAM Registered DIMM Design Standard, Rev 4.04.	MODULE4.20.10	Jan 2010
Release No. 19A. Items 2133.37, 2191.00, 2191.02, 2129.12, 2113.33. Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD	JESD209B	Feb 2010
This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other higher density devices. The purpose of this document is to define the minimum set of requirements for JEDEC compliant 64Mb through 2Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects of this standard will be supported by all LPDDR SDRAM vendors providing compliant devices. (JESD209 was originally numbered as JESD79-4 May 2006 to August 2007, corrected to JESD209 09/17/2007). Patents(): See Document Committee(s): JC-42.3, JC-42.6 Free download. Registration or login required.
Registration - DDR2 SDRAM DIMM (Dual Inline Memory Module) Family with 1.00 mm Contact Centers.	MO-237-G.01	Apr 2011
Item 11.14-128, 11.14-128E Patents(): Hitachi: 5,227,664 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Annex J, R/C J in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification.	MODULE4.20.20.J	May 2011
Release No. 21 Item 2082.93 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex AB, R/C AB in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification	MODULE4.20.20.AB	May 2011
Release No. 21 Item 2202.01 Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE	JESD8-26	Sep 2011
This standard defines the dc and ac input levels, output levels, and input overshoot and undershoot specifications for the 1.2 V High-speed LVCMOS (HS_LVCMOS) interface. The non-terminated interface has a switching range that is nominally expected to be 0 V to 1.2 V and is primarily intended to support communications with Wide I/O SDRAM devices. Committee(s): JC-16 Free download. Registration or login required.
240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification	MODULE4.20.20	Feb 2012
Release No. 22. Item 2082.94A Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

Standards & Documents Search

100 Pin DRAM, SDRAM, and ROM DIMM

144 Pin SDRAM SO-DIMM

VCSDRAM Specific SDRAM Functions

Enhanced SDRAM (ESDRAM) Specific SDRAM Functions

144 Pin and 168 Pin PEMM Families with EDO-DRAM and SDRAM

200 Pin SDRAM DIMM

168 Pin Registered SDRAM DIMM Family

General SDRAM Functions

DDR Specific SDRAM Functions

Registration - 240 pin DDR2 SDRAM, 1.00 mm contact centers, Socket Outline. Item 11.14-061.

200 Pin, PC-2700/PC-2100/PC-1600 Unbuffered SO-DIMM SDRAM Reference Design Specification

Nibble Wide SDRAM

Byte Wide SDRAM

SPD Annex D, DDR Synchronous DRAM (DDR SDRAM)

214-Pin DDR2 SDRAM Unbuffered MicroDIMM Design Specification

100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification

DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS

SDRAM and SGRAM Architectural Operational Features Table of Contents

SPD Annex I, Serial Presence Detect for Virtual Channel SDRAM, Revision 2

Registration - DDR2 SDRAM DIMM (Dual Inline memory Module) Family, Flex-Based, 1.00 mm Contact Centers.

SPD Annex J: Serial Presence Detect for DDR2 SDRAM

144-Pin EP2-2100 DDR2 SDRAM 32b S0DIMM Design Specification, Rev 1.0. Item 2043.09.

Registration - 204 Pin SO-DDR3 SDRAM, 0.60 mm Contact Centers, Socket Outline.

Registration - DDR3 SDRAM DIMM (Dual Inline Memory Module) Family, Flex-Based, 1.00 mm contact Centers

SPECIALITY DDR2-1066 SDRAM

DOUBLE DATA RATE (DDR) SDRAM STANDARD

Word Wide SDRAM.

200-Pin DDR2 SDRAM Unbuffered SODIMM Design Specification

DDR2 Specific SDRAM Function

Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O.

Annex W, R/C W, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.07

Annex Y, R/C Y, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.06

DDR2 SDRAM STANDARD

240-Pin PC2-6400/PC2-5300/PC2-4200/PC2-3200 DDR2 SDRAM Registered DIMM Design Standard, Rev 4.04.

LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD

Registration - DDR2 SDRAM DIMM (Dual Inline Memory Module) Family with 1.00 mm Contact Centers.

Annex J, R/C J in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification.

Annex AB, R/C AB in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification

1.2 V HIGH-SPEED LVCMOS (HS_LVCMOS) INTERFACE

240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification

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