Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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DDR3 SDRAM STANDARD |
JESD79-3F | Jul 2012 |
This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14 Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3 Available for purchase: $247.00 Add to Cart Paying JEDEC Members may login for free access. |
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204-Pin EP3-6400/EP3-8500/EP3-10600/EP3-12800 DDR3 SDRAM 72b-S0-DIMM Design Specification |
MODULE4.20.21 | Aug 2012 |
Release 22. Item 2189.17 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Annex N, R/C N, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2145.22 |
MODULE4.20.20.N | Sep 2012 |
Release No. 22. Item 2145.35 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 1Release Number: 23 |
SPD4.1.2.L-1 | Nov 2013 |
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 1. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01 Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 2Release Number: 23A |
SPD4.1.2.L-2 | Jan 2014 |
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 2. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. (This release is editorial changes only). Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules, Release 6 |
SPD4.1.2.11 | Feb 2014 |
Release No. 24. Item 2065.47A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Registration - 240 Pin DDR3 DIMM (Dual Inline Memory Module) Family with 1.00 mm pitch. DIM |
MO-269J | Apr 2014 |
Item 11.14-163 Free download. Registration or login required. |
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204-Pin DDR3 SDRAM Unbuffered SODIMM Design Specification |
MODULE4.20.18 | May 2014 |
Release No. 24; Item 2114.44 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE 3 SDRAM (LPDDR3) |
JESD209-3C | Aug 2015 |
This document defines the LPDDR3 Standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 4 Gb through 32 Gb for x16 and x32 SDRAM devices. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), LPDDR (JESD209), and LPDDR2 (JESD209-2). Committee Item no. 1798.11D. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.6 Available for purchase: $208.00 Add to Cart Paying JEDEC Members may login for free access. |
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Annex M: Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules, Release 1Release Number: 25 |
SPD4.1.2.M-1 | Nov 2015 |
Committee Document Reference Title: LPDDR3 and LPDDR4 SPD Document Release 1 This Annex describes the serial presence detect (SPD) values for all LPDDR modules. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. The following SPD fields will be documented in the order presented in Section 2, with the exception of bytes 128~255 which are documented in separate sections, one for each family of module types. Further description of Byte 2 is found in Annex A of the SPD standard. Item 2254.01 Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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SPD Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules, Release 6Release Number: 30 |
SPD4.1.2.L-6 | Nov 2020 |
This annex describes the serial presence detect (SPD) values for all DDR4 modules covered in Document Release 6. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. Item 2220.01H.
Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Addendum No. 1 to JESD79-4, 3D STACKED DRAM |
JESD79-4-1B | Feb 2021 |
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58G Committee(s): JC-42.3C Free download. Registration or login required. |
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240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.13 | May 2021 |
Release 31. Item 2167.05 This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.19 | May 2021 |
Release No. 31. Item 2131.03, 2078.04, 2131.06 This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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184 Pin Unbuffered DDR SDRAM DIMM |
MODULE4.5.10 | May 2021 |
Release No.31 This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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184 Pin Unbuffered SDR SDRAM DIMM Family |
MODULE4.5.11 | May 2021 |
Release No.31 This revision contains terminology updates only. Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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240-Pin Unbuffered and Registered DDR2 SDRAM DIMM Family |
MODULE4.5.14 | May 2021 |
Release No. 31 This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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184-Pin PC-2700 SDRAM Unbuffered DIMM - TSOP-Based DRAMs Design Specification |
MODULE4.20.8 | May 2021 |
Release No. 31 This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Low Power Double Data Rate 4 (LPDDR4) |
JESD209-4E | Jun 2024 |
This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 2 Gb through 32 Gb and single channel density ranges from 1 Gb through 16 Gb. Available for purchase: $374.00 Add to Cart Paying JEDEC Members may login for free access. |
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DDR5 SERIAL PRESENCE DETECT (SPD) CONTENTSRelease Number: Release 1.3 |
JESD400-5C | Sep 2024 |
This standard describes the serial presence detect (SPD) values for all DDR5 memory modules. In this context, “modules” applies to memory modules like traditional Dual In-line Memory Modules (DIMMs) or solder-down motherboard applications. The SPD data provides critical information about all modules on the memory channel and is intended to be use by the system's BIOS in order to properly initialize and optimize the system memory channels. Committee(s): JC-45 Free download. Registration or login required. |
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