Global Standards for the Microelectronics Industry
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Displaying 1 - 2 of 2 documents.
Title | Document # | Date |
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REQUIREMENTS FOR MICROELECTRONIC SCREENING AND TEST OPTIMIZATION: |
JEP121B | Dec 2020 |
The purpose of this document provides the basis for the optimization of 100% screening/stress operations and sample inspection test activities. This document is designed to assist the manufacturer in optimizing the test flow while maintaining and/or improving assurance of providing high quality and reliable product in an efficient manner. This will allow for optimization of testing that is not adding value, hence, reducing cycle time and costs. Free download. Registration or login required. |
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HIGH TEMPERATURE STORAGE LIFE |
JESD22-A103E.01 | Jul 2021 |
The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices. The high temperature storage test is typically used to determine the effects of time and temperature, under storage conditions, for thermally activated failure mechanisms and time-to failure distributions of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). Thermally activated failure mechanisms are modeled using the Arrhenius Equation for acceleration. During the test, accelerated stress temperatures are used without electrical conditions applied. This test may be destructive, depending on time, temperature and packaging (if any). Committee(s): JC-14.1 Available for purchase: $55.00 Add to Cart Paying JEDEC Members may login for free access. |