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Displaying 1 - 7 of 7 documents. Show 5 results per page.

Title	Document #	Date
DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS	JESD82-16A.01	Oct 2021
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUA32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document. Committee(s): JC-40, JC-40.3 Free download. Registration or login required.
DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS	JESD82-25.01	Jan 2023
Terminology update. This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32866 registered buffer with parity test for DDR2 RDIMM applications. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:	JESD82-2	Jul 2001
This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module. Committee(s): JC-40 Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD	JESD209B	Feb 2010
This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other higher density devices. The purpose of this document is to define the minimum set of requirements for JEDEC compliant 64Mb through 2Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects of this standard will be supported by all LPDDR SDRAM vendors providing compliant devices. (JESD209 was originally numbered as JESD79-4 May 2006 to August 2007, corrected to JESD209 09/17/2007). Patents(): See Document Committee(s): JC-42.3, JC-42.6 Free download. Registration or login required.
BYTE ADDRESSABLE ENERGY BACKED INTERFACE	JESD245E	Apr 2022
This standard specifies the host and device interface for a DDR4 NVDIMM-N, which is a DIMM that achieves non-volatility by copying SDRAM contents into non-volatile memory (NVM) when host power is lost using an Energy Source managed by either the module or the host. This standard is used in conjunction with JESD248. Item 2233.54G Committee(s): JC-45.6 Free download. Registration or login required.
DDR5 Registering Clock Driver Definition (DDR5RCD02) Release Number: Rev. 1.00	JESD82-512	Feb 2023
This standard defines specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD02 Device ID is DID = 0x0052. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
DDR5 Registering Clock Driver Definition (DDR5RCD04)	JESD82-514.01	Jun 2024
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM applications. The DDR5RCD04 Device ID is DID = 0x0054. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.