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Title	Document #	Date
DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card C Annex Release Number: Version 2.00	JESD305-R8-RCC	Feb 2025
This standard, JESD305-R8-RCC, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card C Annex, defines the design detail of x4, 1 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard. Committee(s): JC-45, JC-45.1 Free download. Registration or login required.
DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard Release Number: Version 2.00	JESD305A	Feb 2025
This standard defines the electrical and mechanical requirements for 288-position, 1.1 Volt (VDD and VDDQ), DDR5 Registered (RDIMM), Double Data Rate (DDR), Synchronous DRAM Dual In-Line Memory Modules (DIMM). These Registered DDR5 SDRAM DIMMs are intended for use in server, workstation, and database environments. Committee(s): JC-45, JC-45.1 Free download. Registration or login required.
DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card D Annex Release Number: Version 2.00	JESD305-R8-RCD	Feb 2025
This standard, JESD305-R8-RCD, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card D Annex, defines the design detail of x8, 1 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard. Committee(s): JC-45, JC-45.1 Free download. Registration or login required.
DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card A Annex Release Number: Version 2.00	JESD305-R8-RCA	Feb 2025
This annex, JESD305-R8-RCA, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card A Annex, defines the design detail of x4, 2 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard. Committee(s): JC-45, JC-45.1 Free download. Registration or login required.
DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card E Annex Release Number: Version 2.00	JESD305-R8-RCE	Feb 2025
This standard, JESD305-R8-RCE, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card E Annex, defines the design detail of x8, 2 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard. Committee(s): JC-45, JC-45.1 Free download. Registration or login required.
DDR5 Registering Clock Driver Definition (DDR5RCD04)	JESD82-514.01	Jun 2024
This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM applications. The DDR5RCD04 Device ID is DID = 0x0054. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
Definition of the SSTUB32869 Registered Buffer with Parity for DDR2 RDIMM Applications	JESD82-27.01	Mar 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32869 registered buffer with parity for driving heavy load on high density DDR2 RDIMM applications. A typical application would be a 36 SDRAM planar DIMM. Committee(s): JC-40 Free download. Registration or login required.
DDR5 Registering Clock Driver Definition (DDR5RCD02) Release Number: Rev. 1.00	JESD82-512	Feb 2023
This standard defines specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD02 Device ID is DID = 0x0052. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
DEFINITION OF THE SSTU32864 1.8 V CONFIGURABLE REGISTERED BUFFER FOR DDR2 RDIMM APPLICATIONS:	JESD82-7A.01	Feb 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32864 configurable registered buffer for DDR2 RDIMM applications. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS	JESD82-25.01	Jan 2023
Terminology update. This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32866 registered buffer with parity test for DDR2 RDIMM applications. Committee(s): JC-40 Free download. Registration or login required.

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JEDEC Education Series: Memory, Mobile & Modules