Global Standards for the Microelectronics Industry
Standards & Documents Search
Displaying 1 - 6 of 6 documents. Show 5 results per page.
Title | Document # | Date |
---|---|---|
DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD |
JEP152 | May 2007 |
This document is the work product of the JC-45.1 DDR2 DIMM Clock Skew Measurement task group.The purpose of this document is to define procedures to measure clock parameters on registered DIMMs using the DDR2 Clock Reference Board. It is NOT the intent of this document to set specification values or validation requirements. Free download. Registration or login required. |
||
DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS |
JESD8-17 | Nov 2004 |
This material is intended to be reflected in supplier specifications for point to point DDR devices ranging from 400 Mb/s to 800 Mb/s operation. It is a method to specify driver impedance with something other than a number that does not nec-essarily define how it operates in a real net This standard addresses this issue using net lengths and specifies how much uncertainty can exist in the data for each speed supported. Free download. Registration or login required. |
||
POD10-1.0 V PSUEDO OPEN DRAIN INTERFACE |
JESD8-25 | Sep 2011 |
This document defines the 1.0 V Pseudo Open Drain Interface family of interface standards, POD10, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Committee(s): JC-16 Free download. Registration or login required. |
||
POD12 ‐ 1.2 V PSEUDO OPEN DRAIN INTERFACE |
JESD8-24 | Aug 2011 |
This document defines the 1.2 V Pseudo Open Drain Interface family of interface standards, POD12, which are generally expected to be implemented with differential amp-based input buffers that, when in single-ended mode, employ an externally supplied (or internal supplied) reference voltage controlled trip-point. Committee(s): JC-16 Free download. Registration or login required. |
||
POD15 - 1.5 V PSEUDO OPEN DRAIN I/O |
JESD8-20A.01 | Aug 2022 |
Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily used to communicate with GDDR4 and GDDR5 SGRAM devices. Item 135.01 Committee(s): JC-16 Free download. Registration or login required. |
||
POD18 - 1.8 V PSEUDO OPEN DRAIN I/O |
JESD8-19 | Dec 2006 |
This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.8 V Pseudo Open Drain I/Os. The 1.8 V Pseudo Open Drain interface, also known as POD18, is primarily used to communicate with GDDR3 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required. |