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Displaying 1 - 5 of 10 documents. Show 5 results per page.

Title	Document #	Date
PACKAGE WARPAGE MEASUREMENT OF SURFACE-MOUNT INTEGRATED CIRCUITS AT ELEVATED TEMPERATURE	JESD22-B112B	Aug 2018
The purpose of this test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of environmental conditions experienced during the surface-mount soldering operation. Committee(s): JC-14.1 Free download. Registration or login required.
Registration - 204 Pin DDR3 SODIMM w/ 0.60 mm Pitch. DIM	MO-268E	Mar 2014
Item 11.14-151 Patents(): Hatachi: 5,227,664 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Upper PoP Package, Square, Fine Pitch, Ball Grid Array (BGA), 0.65 and 0.50 mm and 0.40 mm Pitch. POP-XFBGA. Status: Rescinded March 2018	MO-273C	Mar 2011
The information contained in MO-273, has been moved to 3 different MO's as follows: The 0.40 mm pitch has been moved to MO-317. The 0.50 mm pitch has been moved to MO-321. The 0.65 mm pitch has been moved to MO-322. Item 11.11-941(E) Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page
Standard Practices and Procedures - Reflow Flatness Requirements for Ball Grid Array Packages. Item 11.2-783	SPP-024A	Mar 2009
This document states the procedures for using component land side flatness during simulated reflow as an alternative to coplanarity in certain limited cases for BGA components. Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
THERMAL MODELING OVERVIEW	JESD15	Oct 2008
This document and the associated series of documents are intended to promote the continued development of modeling methods, while providing a coherent framework for their use by defining a common vocabulary to discuss modeling, creating requirements for what information should be included in a thermal modeling report, and specifying modeling procedures, where appropriate, and validation methods. This document provides an overview of the methodology necessary for performing meaningful thermal simulations for packages containing semiconductor devices. The actual methodology components are contained in separate detailed documents. Committee(s): JC-15, JC-15.1 Free download. Registration or login required.

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