Global Standards for the Microelectronics Industry
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Displaying 1 - 5 of 10 documents. Show 5 results per page.
Title | Document # |
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PACKAGE WARPAGE MEASUREMENT OF SURFACE-MOUNT INTEGRATED CIRCUITS AT ELEVATED TEMPERATURE |
JESD22-B112B | Aug 2018 |
The purpose of this test method is to measure the deviation from uniform flatness of an integrated circuit package body for the range of environmental conditions experienced during the surface-mount soldering operation. Committee(s): JC-14.1 Free download. Registration or login required. |
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Registration - 204 Pin DDR3 SODIMM w/ 0.60 mm Pitch. DIM |
MO-268E | Mar 2014 |
Item 11.14-151 Patents(): Hatachi: 5,227,664 Committee(s): JC-11.14 Free download. Registration or login required. |
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Registration - Upper PoP Package, Square, Fine Pitch, Ball Grid Array (BGA), 0.65 and 0.50 mm and 0.40 mm Pitch. POP-XFBGA.Status: Rescinded March 2018 |
MO-273C | Mar 2011 |
The information contained in MO-273, has been moved to 3 different MO's as follows: The 0.40 mm pitch has been moved to MO-317. The 0.50 mm pitch has been moved to MO-321. The 0.65 mm pitch has been moved to MO-322. Item 11.11-941(E) |
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Standard Practices and Procedures - Reflow Flatness Requirements for Ball Grid Array Packages. Item 11.2-783 |
SPP-024A | Mar 2009 |
This document states the procedures for using component land side flatness during simulated reflow as an alternative to coplanarity in certain limited cases for BGA components. Free download. Registration or login required. |
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COMPACT THERMAL MODEL OVERVIEW |
JESD15-1 | Oct 2008 |
This document should be used in conjunction with the master document, JESD15, and JESD15-2, and subsidiary documents as they become available. This document is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents. At present, there are two such documents; JESD15-3, and JESD15-4. Free download. Registration or login required. |