Global Standards for the Microelectronics Industry
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Displaying 1 - 5 of 9 documents. Show 5 results per page.
Title | Document # | Date |
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Power Cycling |
JESD22-A122B | Nov 2023 |
This Test Method establishes a uniform method for performing solid state device package power cycling stress test. Free download. Registration or login required. |
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Registration - 204 Pin DDR3 SODIMM w/ 0.60 mm Pitch. DIM |
MO-268E | Mar 2014 |
Item 11.14-151 Patents(): Hatachi: 5,227,664 Committee(s): JC-11.14 Free download. Registration or login required. |
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Registration - Upper PoP Package, Square, Fine Pitch, Ball Grid Array (BGA), 0.65 and 0.50 mm and 0.40 mm Pitch. POP-XFBGA.Status: Rescinded March 2018 |
MO-273C | Mar 2011 |
The information contained in MO-273, has been moved to 3 different MO's as follows: The 0.40 mm pitch has been moved to MO-317. The 0.50 mm pitch has been moved to MO-321. The 0.65 mm pitch has been moved to MO-322. Item 11.11-941(E) |
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Standard Practices and Procedures - Reflow Flatness Requirements for Ball Grid Array Packages. Item 11.2-783 |
SPP-024A | Mar 2009 |
This document states the procedures for using component land side flatness during simulated reflow as an alternative to coplanarity in certain limited cases for BGA components. Free download. Registration or login required. |
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THERMAL MODELING OVERVIEW |
JESD15 | Oct 2008 |
This document and the associated series of documents are intended to promote the continued development of modeling methods, while providing a coherent framework for their use by defining a common vocabulary to discuss modeling, creating requirements for what information should be included in a thermal modeling report, and specifying modeling procedures, where appropriate, and validation methods. This document provides an overview of the methodology necessary for performing meaningful thermal simulations for packages containing semiconductor devices. The actual methodology components are contained in separate detailed documents. Free download. Registration or login required. |