Standards & Documents Search

Displaying 1 - 4 of 4 documents.

Title	Document #	Date
48 Lead, Very, Very Thin Small Outline Package, Type 1. WR-PDSO1, WSOP1. Item 11.11-701.	MO-259-A	Mar 2005
Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
NAND Flash Interface Interoperability	JESD230G	Oct 2024
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Committee(s): JC-42, JC-42.4 Free download. Registration or login required.
SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD	JESD218B.03	Aug 2024
Terminology Update, see Annex. This standard defines JEDEC requirements for solid state drives. For each defined class of solid state drive, the standard defines the conditions of use and the corresponding endurance verification requirements. Although endurance is to be rated based upon the standard conditions of use for the class, the standard also sets out requirements for possible additional use conditions as agreed to between manufacturer and purchaser. Revision A includes further information on SSD Capacity. Items 303.19, 303.20, 303.21, 303.22, 303.23, 303.26, 303.27, 303.28, and 303.32 Committee(s): JC-64.8 Available for purchase: $76.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
MCP and Discrete e•MMC, e•2MMC, and UFS Release Number: 33	MCP3.12.1-1	Jun 2024
Item 142.12 This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution. Committee(s): JC-64.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.