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Title	Document #	Date
TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATION:	JESD57A	Nov 2017
This test method defines requirements and procedures for ground simulation and single event effects (SEE) and implementation of the method in testing integrated circuits. This standard is valid when using a cyclotron or Van de Graaff accelerator. Microcircuits under test must be delidded. The ions used at the facilities have an atomic number Z > 2. It does not apply to SEE testing that uses protons, neutrons, or other lighter particles. This standard is designed to eliminate any misunderstanding between users of the method and test facilities, to minimize delays, and to promote standardization of testing and test data. Committee(s): JC-13.4 Free download. Registration or login required.
Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices	JEP151A	Jan 2022
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications. Committee(s): JC-14.1 Free download. Registration or login required.
TEST PROCEDURES FOR CUSTOM MONOLITHIC MICROCIRCUITS - SUPERSEDED BY MIL-PRF-38535C. Status: RescindedJun-96	JEP111	Jan 1986
Committee(s): JC-13, JC-13.2
TEST PROCEDURES FOR VERIFICATION OF MAXIMUM RATINGS OF POWER TRANSISTORS: Status: ReaffirmedSeptember 1981, April 1999	JEP65	Dec 1967
This publication describes tests which are intended to represent the verification of maximum ratings for data sheets; they are not tests for performance or quality level. This material is to be used in conjunction with formats developed for device registration and defining data. Committee(s): JC-25 Free download. Registration or login required.
TEST STANDARD FOR THE MEASUREMENT OF PROTON RADIATION SINGLE EVENT EFFECTS IN ELECTRONIC DEVICES	JESD234	Oct 2013
This test standard defines the requirements and procedures for 40 to 500 MeV proton irradiation of electronic devices for Single Event Effects (SEE), and reporting the results. Protons are capable of causing SEE by both direct and indirect ionization, however, in this energy range, indirect ionization will be the dominant cause of SEE [1-3]. Indirect ionization is produced from secondary particles of proton/material nuclear reactions, where the material is Si or any other element present in the semiconductor. Direct proton ionization is thought to be a minor source of SEE, at these energies. This energy range is also selected to coincide with the commonly used proton facilities, and result in the fewest energy dependent issues during test. Committee(s): JC-13, JC-13.4 Free download. Registration or login required.
TEST TRACE FOR 64 GB - 128 GB SSD	JESD219A_TT	Jul 2012
The Test Trace file is a supporting file for implementation of the endurance verification client workload and is used in conjunction with JESD219A. This Test Trace is derived from the 128 GB Master Trace using the compression method described in JESD219 to enable testing on SSDs with a capacity range of 64 GB to 128 GB. All characteristics of this Test Trace are identical to the Master Trace except that the maximum LBA represents an SSD user capacity of 64 GB. Committee(s): JC-64.8 Free download. Registration or login required.
THE MEASUREMENT OF SMALL-SIGNAL VHF-UHF TRANSISTOR ADMITTANCE PARAMETERS: Status: ReaffirmedApril 1981, April 1999, March 2009	JESD372	May 1970
This standard describes the method to be used for the measurement of small-signal VHF-UHF transistor admittance parameters, in preparing data sheets for JEDEC registration of low power transistors. Formerly known as RS-372 and/or EIA-372 Committee(s): JC-25 Free download. Registration or login required.
THE MEASUREMENT OF SMALL-SIGNAL VHF-UHF TRANSISTOR SHORT-CIRCUIT FORWARD CURRENT TRANSFER RATIO: Status: ReaffirmedApril 1981, April 1999, March 2009	JESD371	Feb 1970
This standard describes the method to be used for the measurement of small-signal VHF-UHF transistor short-circuit forward current transfer ratio, in preparing data sheets for JEDEC registration of low power transistors. Formerly known as RS-371 and/or EIA-371. Committee(s): JC-25 Free download. Registration or login required.
THE MEASUREMENT OF TRANSISTOR EQUIVALENT NOISE VOLTAGE AND EQUIVALENT NOISE CURRENT AT FREQUENCIES OF UP TO 20 kHz Status: Reaffirmed April 1981, April 1999, March 2009	JESD354	Apr 1968
This standard provides a method for determining values, for device registration purposes, for transistor equivalent noise voltage and equivalent noise current at frequencies up to 20 kHz. This method is applicable to transistors whose noise has a Gaussian, flat (white) or I/f power distribution. Formerly known as RS-354 and/or EIA-354 Committee(s): JC-25 Free download. Registration or login required.
THE MEASUREMENT OF TRANSISTOR NOISE FIGURE AT FREQUENCIES UP TO 20 kHz BY SINUSOIDAL SIGNAL-GENERATOR METHOD Status: Reaffirmed April 1981, April 1999, March 2009	JESD353	Apr 1968
This noise measurement method applies to transistors whose noise has a Gaussian power distribution, to transistors whose noise has a flat (white) power distribution, and to transistors whose noise has a l/f (power inversely proportional to frequency) power distribution. Formerly known as RS-353 and/or EIA-353 Committee(s): JC-25 Free download. Registration or login required.
THERMAL IMPEDANCE MEASUREMENT FOR INSULATED GATE BIPOLAR TRANSISTORS - (Delta VCE(on) Method)	JESD24-12	Jun 2004
The purpose of this test method is to measure the thermal impedance of the IGBT (Insulated Gate Bipolar Transistor) under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity of the collector-emitter on voltage, VCE(on), is used as the junction temperature indicator. This is an alternative method to JEDEC Standard No. 24-6. Committee(s): JC-25 Free download. Registration or login required.
THERMAL MODELING OVERVIEW	JESD15	Oct 2008
This document and the associated series of documents are intended to promote the continued development of modeling methods, while providing a coherent framework for their use by defining a common vocabulary to discuss modeling, creating requirements for what information should be included in a thermal modeling report, and specifying modeling procedures, where appropriate, and validation methods. This document provides an overview of the methodology necessary for performing meaningful thermal simulations for packages containing semiconductor devices. The actual methodology components are contained in separate detailed documents. Committee(s): JC-15, JC-15.1 Free download. Registration or login required.
THERMAL RESISTANCE AND THERMAL IMPEDANCE TEST METHODS FOR STUD AND BASE-MOUNTED RECTIFIER DIODES AND THYRISTORS Status: Rescinded	JEP88	Jan 1974
Committee(s): JC-22.1
THERMAL RESISTANCE FOR TEST METHODS FOR SIGNAL DIODES - SUPERSEDED BY EIA-531, July 1986. See JESD531, April 2002. Status: Rescinded	JEP90	Sep 1983
Committee(s): JC-22.4 Free download. Registration or login required.
THERMAL RESISTANCE MEASUREMENTS OF CONDUCTION COOLED POWER TRANSISTORS: Status: ReaffirmedApril 1981, April 2001	JESD313-B	Oct 1975
This standard provides a test method for measuring thermal resistance for conduction cooled power transistors. Committee(s): JC-25 Free download. Registration or login required.
THERMAL RESISTANCE TEST METHOD FOR SIGNAL AND REGULATOR DIODES (FORWARD VOLTAGE, SWITCHING METHOD): Status: ReaffirmedApril 1999, April 2002	JESD531	Jul 1986
This standard describes a test method for measuring the thermal resistance of signal and regulator diodes. The need for modification of this test method arose out of the limited description that existed earlier for both signal and regulator diode applications in testing for thermal resistance. Previously published as ID-13. ANSI/EIA-531-1986 (July) expired June 1996. Became JESD531 after reaffirmation April 2002. Committee(s): JC-22.4 Free download. Registration or login required.
THERMAL SHOCK	JESD22-A106B.02	Jan 2023
This test is conducted to determine the robustness of a device to sudden exposure to extreme changes in temperature and to the effect of alternate exposures to these extremes. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
THERMAL TEST CHIP GUIDELINE (WIRE BOND AND FLIP CHIP)	JESD51-4A	Jul 2019
The purpose of this document is to provide a design guideline for thermal test chips used for integrated circuit (IC) and transistor package thermal characterization and investigations. The intent of this guideline is to minimize the differences in data gathered due to nonstandard test chips and to provide a well-defined reference for thermal investigations. Committee(s): JC-15 Free download. Registration or login required.
THERMAL TEST CHIP GUIDELINE (WIRE BOND TYPE CHIP)- SUPERSEDED BY JESD51-4, September 1997. Status: ElevatedSeptember 1997	JEP129	Feb 1997
Committee(s): JC-15.1 Free download. Registration or login required.
THERMAL TEST ENVIRONMENT MODIFICATIONS FOR MULTICHIP PACKAGES	JESD51-31	Jul 2008
This document specifies the appropriate modifications needed for Multi-Chip Packages to the thermal test environmental conditions specified in the JESD51 series of specifications. The data obtained from methods of this document are the raw data used to document the thermal performance of the package. The use of this data will be documented in JESD51-XX, Guideline to Support Effective Use of MCP Thermal Measurements which is being prepared. Committee(s): JC-15 Free download. Registration or login required.

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JEDEC Education Series: Memory, Mobile & Modules