Global Standards for the Microelectronics Industry
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Displaying 1 - 4 of 4 documents.
| Title | Document # | Date |
|---|---|---|
Silicon Pad Sequence (x16/x32 LPDRAM, x16 PSRAM, x16 NAND). Item JC-63-029 |
MCP3.12.3 | Nov 2006 |
Release No. 16A Committee(s): JC-63 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Package-on-Package (PoP) and Internal Stacked Module (ISM) |
MCP3.12.2 | Jan 2012 |
Release No. 22. Committee(s): JC-63 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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EXTENSION TO JESD51 THERMAL TEST BOARD STANDARDS TO ACCOMMODATE MULTI-CHIP PACKAGES |
JESD51-32 | Dec 2010 |
This document addresses the need for extending the existing thermal test board standards to accommodate the potential of higher electrical connection needs of multi-chip packages (MCPs) and the associated wire routing to implement these connections. The extensions described in this standard are also applicable to single chip packages needing more than 36 electrical connections for the test. Committee(s): JC-15 Free download. Registration or login required. |
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MCP and Discrete e•MMC, e•2MMC, and UFSRelease Number: 33 |
MCP3.12.1-1 | Jun 2024 |
Item 142.12 This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.
Committee(s): JC-64.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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