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Title	Document #	Date
Registration - Standard and Low, Fine Pitch Rectangular Ball Grid Array Family, 0.65 mm Pitch. FR-XBGA, LFR-XBGA.	MO-301A	May 2010
Item 11.11-828 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 240 Pin DDR3 DIMM (Dual Inline Memory Module) Family with 1.00 mm pitch. DIM	MO-269J	Apr 2014
Item 11.14-163 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
LRDIMM DDR3 MEMORY BUFFER (MB)	JESD82-30	Oct 2014
The Load Reduced DIMM (LRDIMM) Memory Buffer (MB) supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (SSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components. The Memory Buffer interface is responsible for memory requests to and from the local DIMM. LRDIMM provides a high memory bandwidth, large capacity channel solution for DDR3 main memory systems. LRDIMM uses commodity DRAMs isolated from the channel behind the Memory Buffer on the DIMM. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
Annex D, R/C D, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification Release Number: 30	MODULE4.20.27.D	Dec 2020
This specification defines the electrical and mechanical requirements for Raw Card D, 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Item 2204.23 Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex B, Raw Card B, in 288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification Release Number: 30	MODULE4.20.27.B	Dec 2020
This specification defines the electrical and mechanical requirements for Raw Card B, 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Item 2204.24. Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
288-Pin, 1.2 V (VDD), PC4-1600/PC4-1866/PC4-2133/PC4-2400/PC4-2666/PC4-3200 DDR4 SDRAM Load Reduced DIMM Design Specification Release Number: 25	MODULE4.20.27	Aug 2015
Item 2204.07 This specification defines the electrical and mechanical requirements for 288-pin, 1.2 Volt (VDD), Load Reduced, Double Data Rate, Synchronous DRAM Dual In-Line Memory Modules (DDR4 SDRAM LRDIMMs). These DDR4 Load Reduced DIMMs (LRDIMMs) are intended for use as main memory when installed in PCs. Committee(s): JC-45.4 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.