Global Standards for the Microelectronics Industry
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Displaying 1 - 2 of 2 documents.
| Title | Document # | Date |
|---|---|---|
HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT |
JESD8-22B | Apr 2014 |
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. Committee(s): JC-16 Free download. Registration or login required. |
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Annex M: Serial Presence Detect (SPD) for LPDDR3 and LPDDR4 SDRAM Modules, Release 1Release Number: 25 |
SPD4.1.2.M-1 | Nov 2015 |
Committee Document Reference Title: LPDDR3 and LPDDR4 SPD Document Release 1 This Annex describes the serial presence detect (SPD) values for all LPDDR modules. Differences between module types are encapsulated in subsections of this annex. These presence detect values are those referenced in the SPD standard document for ‘Specific Features’. The following SPD fields will be documented in the order presented in Section 2, with the exception of bytes 128~255 which are documented in separate sections, one for each family of module types. Further description of Byte 2 is found in Annex A of the SPD standard. Item 2254.01 Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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