Standards & Documents Search

Displaying 1 - 4 of 4 documents.

Title	Document #	Date
Package-on-Package (PoP) and Internal Stacked Module (ISM)	MCP3.12.2	Jan 2012
Release No. 22. Item 48.18, 48.24, 48.26, 38.21b, 48.06a, 38.26, 48.28, 48.29 Committee(s): JC-63 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE 2 (LPDDR2)	JESD209-2F	Jun 2013
This document defines the LPDDR2 specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. This standard covers the following technologies: LPDDR2-S2A, LPDDR2-S2B, LPDDR2-S4A, LPDDR2-S4B, LPDDR2-N-A, and LPDDR2-N-B. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8, x16, and x32 SDRAM devices as well as 64 Mb through 32 Gb for x8, x16, and x32 for NVM devices. Item 1725.01G. Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.6 Free download. Registration or login required.
HSUL_12 LPDDR2 AND LPDDR3 I/O WITH OPTIONAL ODT	JESD8-22B	Apr 2014
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. Committee(s): JC-16 Free download. Registration or login required.
Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFS Release Number: 31	MCP3.12.1	Mar 2021
Item 142.01, 142.02.This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution. Committee(s): JC-64.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.