Global Standards for the Microelectronics Industry
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Displaying 1 - 9 of 9 documents. Show 5 results per page.
Title | Document # | Date |
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STANDARD - FBDIMM Socket Insertion and Extraction Force Gauge. Item 11.14-083(S) |
GS-004A | Oct 2006 |
Committee(s): JC-11 Free download. Registration or login required. |
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Registration - FBDIMM, 240 Position Socket Outline with 1.00 mm Contact Centers. Item 11.14-082 and 11.14-087. |
SO-003B | Aug 2006 |
Committee(s): JC-11 Free download. Registration or login required. |
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Registration - 240 Pin FBDIMM 1.00 mm Contact Centers, Press Fit Socket Outline. SKT. Item 11.14-113 |
SO-013A | Sep 2007 |
Committee(s): JC-11 Free download. Registration or login required. |
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Registration - FBDIMM (Fully Buffered Dual Inline Memory Module) Family, 1.00 mm Contact Centers. |
MO-256-F | Jun 2007 |
Item 11.14-108 Committee(s): JC-11.14 Free download. Registration or login required. |
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Registration - FBDIMM (Dual In-Line Memory Module) Family, Flex-Based, 1.00 mm Contact Centers. |
MO-282-A | Jan 2007 |
Item 11.14-099 Patents(): STAKTEK: See Outline Committee(s): JC-11 Free download. Registration or login required. |
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FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V |
JESD8-18A | Mar 2008 |
This specification defines the high-speed differential point-to-point signaling link for FBDIMM, operating at the buffer supply voltage of 1.5V that is provided at the FBDIMM DIMM connector. This specification also applies to FBDIMM host chips which may operate with a different supply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit-stream. The first generation FBDIMM link is being specified to operate from 3.2 to 4.8 Gb/s. The specifications are defined for three distinct bit-rates of operation: 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-16 Free download. Registration or login required. |
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FBDIMM STANDARD: DDR2 SDRAM FULLY BUFFERED DIMM (FBDIMM) DESIGN STANDARD |
JESD205 | Mar 2007 |
This standard defines the electrical and mechanical requirements for 240-pin, PC2-4200/PC2-5300/PC2-6400, 72 bit-wide, Fully Buffered Double Data Rate Synchronous DRAM Dual In-Line Memory Modules (DDR2 SDRAM FB-DIMMs).These SDRAM FB-DIMMs are intended for use as main memory when installed in systems such as servers and workstations. PC2-4200/PC2-5300/PC2-6400 refers to the DIMM naming convention in which PC2-4200/PC2-5300/PC2-6400 indicates a 240-pin DDR2 DIMM running at 266/333/400 MHz DRAM clock speed and offering 4266/5333/6400 MB/s bandwidth. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Free download. Registration or login required. |
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FBDIMM: ADVANCED MEMORY BUFFER (AMB) |
JESD82-20A.01 | Jan 2023 |
This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required. |
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SPD Annex G, Serial Presence Detect for FBDIMM, Revision 1.1 |
SPD4.1.2.7 | Jun 2006 |
Release No. 16A. Item 2003.02A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |