Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATIONStatus: Reaffirmed January 2024 |
JEP155B | Jul 2018 |
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD level requirements. It will be shown through this document why realistic modifying of the ESD target levels for component level ESD is not only essential but is also urgent. The document is organized in different sections to give as many technical details as possible to support the purpose given in the abstract. In June 2009 the formulating committee approved the addition of the ESDA logo on the covers of this document. Please see Annex C for revision history. Reaffirmed: January 2024 Free download. Registration or login required. |
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RECOMMENDED ESD-CDM TARGET LEVELS |
JEP157A | Apr 2022 |
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. Free download. Registration or login required. |
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SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNSThis is an editorial revision, details can be found in Annex F. |
JEP162A.01 | Jan 2021 |
This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Free download. Registration or login required. |
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Requirements for Handling Electrostatic-Discharge-Sensitive (ESDS) Devices |
JESD625C.01 | Mar 2024 |
This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM). Free download. Registration or login required. |
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FIELD-INDUCED CHARGED-DEVICE MODEL TEST METHOD FOR ELECTROSTATIC DISCHARGE WITHSTAND THRESHOLDS OF MICROELECTRONIC COMPONENTSStatus: Rescinded February 2020 |
JESD22-C101F | Oct 2013 |
The material in this test method has been superseded by JS-002-2018, published January 2019, which in turn has been superseded by JS-002-2022, published January 2023. |
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SYSTEM LEVEL ESD PART 1: COMMON MISCONCEPTIONS AND RECOMMENDED BASIC APPROACHESStatus: ReaffirmedApril 2023 |
JEP161 | Jan 2011 |
This report is the first part of a two part document. Part I will primarily address hard failures characterized by physical damage to a system (failure category d as classified by IEC 61000-4-2). Soft failures, in which the system’s operation is upset without physical damage, are also critical and predominant in many cases. Free download. Registration or login required. |
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DISCONTINUING USE OF THE MACHINE MODEL FOR DEVICE ESD QUALIFICATIONStatus: Reaffirmed September 2020 |
JEP172A | Jul 2015 |
Over the last several decades the so called "machine model" (aka MM) and its application to the required ESD component qualification has been grossly misunderstood. The scope of this JEDEC document is to present evidence to discontinue use of this particular model stress test without incurring any reduction in the IC component's ESD reliability for manufacturing. In this regard, the document's purpose is to provide the necessary technical arguments for strongly recommending no further use of this model for IC qualification. The published document should be used as a reference to propagate this message throughout the industry. Committee(s): JC-14.3 Free download. Registration or login required. |
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ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING MACHINE MODEL (MM)This document is inactive as of September 2016 |
JESD22-A115C | Nov 2010 |
JESD22-A115 is a reference document; it is not a requirement per JESD47 (Stress Test Driven Qualification of Integrated Circuits). Machine Model (MM) as described in JESD22-A115 should not be used as a requirement for integrated circuit ESD qualification. Only human-body model (HBM) and charged-device model (CDM) are the necessary ESD qualification test methods as specified in JESD47. Refer to JEP172: Discontinuing Use of the Machine Model for Device ESD Qualification for more information. Committee(s): JC-14.1 |
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JOINT JEDEC/ESDA STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TEST - HUMAN BODY MODEL (HBM) - COMPONENT LEVEL |
JS-001-2023 | Jul 2023 |
This standard establishes the procedure for testing, evaluating, and classifying components and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined human body model (HBM) electrostatic discharge (ESD). The purpose (objective) of this standard is to establish a test method that will replicate HBM failures and provide reliable, repeatable HBM ESD test results from tester to tester, regardless of component type. Repeatable data will allow accurate classifications and comparisons of HBM ESD sensitivity levels. NOTE Data previously generated with testers meeting all waveform criteria of ANSI/ESD STM5.1-2007 or JESD22A-114F shall be considered valid test data. Also available JTR-001-01-12: User Guide of ANSI/ESDA/JEDEC JS-001, Human Body Model Testing of Integrated Circuits Free download. Registration or login required. |
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ESDA/JEDEC JOINT STANDARD FOR ELECTROSTATIC DISCHARGE SENSITIVITY TESTING – CHARGED DEVICE MODEL (CDM) – DEVICE LEVEL |
JS-002-2022 | Jun 2023 |
This standard establishes the procedure for testing, evaluating, and classifying devices and microcircuits according to their susceptibility (sensitivity) to damage or degradation by exposure to a defined field-induced charged device model (CDM) electrostatic discharge (ESD). All packaged semiconductor devices, thin film circuits, surface acoustic wave (SAW) devices, opto-electronic devices, hybrid integrated circuits (HICs), and multi-chip modules (MCMs) containing any of these devices are to be evaluated according to this standard. This test method combines the main features of JEDEC JESD22-C101 and ANSI/ESD S5.3.1. Free download. Registration or login required. |
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A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces |
JEP196 | Nov 2023 |
This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces. Free download. Registration or login required. |