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Title	Document #	Date
DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD	JEP152	May 2007
This document is the work product of the JC-45.1 DDR2 DIMM Clock Skew Measurement task group.The purpose of this document is to define procedures to measure clock parameters on registered DIMMs using the DDR2 Clock Reference Board. It is NOT the intent of this document to set specification values or validation requirements. Committee(s): JC-45, JC-45.1 Free download. Registration or login required.
Dynamic Random Access Memory (DRAM) Table of Contents	DRAM3.9.TOC	Jul 1997
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Bit Wide DRAM	DRAM3.9.1	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Nibble Wide DRAM	DRAM3.9.2	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide DRAM	DRAM3.9.4	Jul 2000
Release No. 10 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Byte Wide DRAM	DRAM3.9.3	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DRAM Operational Features	DRAM3.9.5	Feb 2000
Release No.9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Word Wide Graphics DRAM	MPDRAM3.10.3	Jan 2004
Release No.13 Committee(s): JC-42.3, JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
88 Pin DRAM Card Status: Reaffirmed	MODULE4.4.3	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
72 Pin DRAM SIMM	MODULE4.4.2	Dec 1997
Release No.8 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
72 Pin DRAM SO-DIMM	MODULE4.4.4	Jun 1997
Release No. 9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin DRAM DIMM	MODULE4.5.1	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin Unbuffered DRAM DIMM	MODULE4.5.3	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
144 Pin DRAM SO-DIMM	MODULE4.5.5	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS	JESD8-17	Nov 2004
This material is intended to be reflected in supplier specifications for point to point DDR devices ranging from 400 Mb/s to 800 Mb/s operation. It is a method to specify driver impedance with something other than a number that does not nec-essarily define how it operates in a real net This standard addresses this issue using net lengths and specifies how much uncertainty can exist in the data for each speed supported. Committee(s): JC-16.1, JC-16 Free download. Registration or login required.
POD18 - 1.8 V PSEUDO OPEN DRAIN I/O	JESD8-19	Dec 2006
This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.8 V Pseudo Open Drain I/Os. The 1.8 V Pseudo Open Drain interface, also known as POD18, is primarily used to communicate with GDDR3 SGRAM devices. Committee(s): JC-16 Free download. Registration or login required.
POD15 - 1.5 V PSEUDO OPEN DRAIN I/O	JESD8-20A.01	Aug 2022
Terminology Update. This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedance, and the termination and calibration scheme for 1.5 V Pseudo Open Drain I/Os. The 1.5 V Pseudo Open Drain interface, also known as POD15, is primarily used to communicate with GDDR4 and GDDR5 SGRAM devices. Item 135.01 Committee(s): JC-16 Free download. Registration or login required.
100 Pin DRAM, SDRAM, and ROM DIMM	MODULE4.4.8	Dec 1997
Release No. 8 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184-Pin PC-2700 SDRAM Unbuffered DIMM - TSOP-Based DRAMs Design Specification	MODULE4.20.8	May 2021
Release No. 31 This revision contains terminology updates only. Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DOUBLE DATA RATE (DDR) SDRAM STANDARD	JESD79F	Feb 2008
This comprehensive standard defines all required aspects of 64Mb through 1Gb DDR SDRAMs with X4/X8/X16 data interfaces, including features, functionality, ac and dc parametrics, packages and pin assignments. This scope will subsequently be expanded to formally apply to x32 devices, and higher density devices as well The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64Mb through 1Gb, X4/X8/X16 DDR SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR SDRAM vendors providing JEDEC compliant devices. Committee(s): JC-42.3 Free download. Registration or login required.

Standards & Documents Search

DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD

Dynamic Random Access Memory (DRAM) Table of Contents

Bit Wide DRAM

Nibble Wide DRAM

Word Wide DRAM

Byte Wide DRAM

DRAM Operational Features

Word Wide Graphics DRAM

88 Pin DRAM Card

72 Pin DRAM SIMM

72 Pin DRAM SO-DIMM

168 Pin DRAM DIMM

168 Pin Unbuffered DRAM DIMM

144 Pin DRAM SO-DIMM

DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS

POD18 - 1.8 V PSEUDO OPEN DRAIN I/O

POD15 - 1.5 V PSEUDO OPEN DRAIN I/O

100 Pin DRAM, SDRAM, and ROM DIMM

184-Pin PC-2700 SDRAM Unbuffered DIMM - TSOP-Based DRAMs Design Specification

DOUBLE DATA RATE (DDR) SDRAM STANDARD

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