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Title	Document #	Date
278 Pin Buffered SDRAM DIMM	MODULE4.6.1	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
112 Pin MPDRAM DIMM	MODULE4.4.6	Jun 1997
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin DRAM DIMM	MODULE4.5.1	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin Unbuffered DRAM DIMM	MODULE4.5.3	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS:	JESD82	Jul 2000
This specification is a reference for Registered DDR DIMM designers. JESD82 defines the physical, electrical, interface and timing requirements of a 1:10 PLL clock driver for DDR Registered DIMMs from DDR200 to DDR266 as refined in revision C of JEDEC Standard 21-C (JESD21-C). JESD82 was also written to meet the future performance requirements of Registered DIMMs for DDR300 and DDR333. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:	JESD82-2	Jul 2001
This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module. Committee(s): JC-40 Free download. Registration or login required.
200 Pin SDRAM DIMM	MODULE4.5.2	Oct 2001
Release No.11 Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin Registered SDRAM DIMM Family	MODULE4.5.7	Oct 2001
Release No.11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION	JESD82-5	Jul 2002
This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently under development for DDR2 support devices. Committee(s): JC-40 Free download. Registration or login required.
Registration - Addition of 172 pin Micro DIMM variations and modification of terminal postional tolerance to Micro DIMM registration. Item 11.14-049.	MO-214-B	Sep 2002
0.50 mm Lead Centers Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 244 Pin DDR2/DDR3 Mini DIMM with 0.60 mm Lead Centers Socket Outline. Item 11.14-122.	SO-002B	Oct 2003
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
DIMM Design Files	DIMM Homepage	Dec 2003
These reference files are registered as industry accepted examples for use by manufacturers. Please be sure to read the license agreement prior to downloading files. Design Files (Gerber Files) have been developed in accordance with the JEDEC Manual of Operation and Procedure. Committee(s): JC-42, JC-45 See DIMM Homepage information
DEFINITION OF CU878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-11	Sep 2004
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CU878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CU878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.3 Free download. Registration or login required.
100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification	MODULE4.20.9	Nov 2004
Release No. 14 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - 200 pin DDR MiniDIMM. 0.60 mm Lead Centers. Item 11.14-069.	MO-258-A	Dec 2004
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 200 pin Mini DIMM with 0.60 mm Lead Centers Socket Outline	SO-005A	Jan 2005
Item 11.14-070 Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Dual Inline Memory Module (DIMM) Family, 184 Pin DDR w/ 1.27 mm Contact Centers. Item 11.14-078	MO-206-E	Jan 2006
Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Standard - DDR3 DIMM Socket Insertion and Extraction Force Gauge. Item 11.14-098	GS-005A	Jul 2006
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD - FBDIMM Socket Insertion and Extraction Force Gauge. Item 11.14-083(S)	GS-004A	Oct 2006
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR2 SDRAM DIMM (Dual Inline memory Module) Family, Flex-Based, 1.00 mm Contact Centers.	MO-281-A	Nov 2006
Item 11.14-100 Patents(): STAKTEK: See Outline Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.

Standards & Documents Search

278 Pin Buffered SDRAM DIMM

112 Pin MPDRAM DIMM

168 Pin DRAM DIMM

168 Pin Unbuffered DRAM DIMM

DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS:

STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:

200 Pin SDRAM DIMM

168 Pin Registered SDRAM DIMM Family

STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION

Registration - Addition of 172 pin Micro DIMM variations and modification of terminal postional tolerance to Micro DIMM registration. Item 11.14-049.

Registration - 244 Pin DDR2/DDR3 Mini DIMM with 0.60 mm Lead Centers Socket Outline. Item 11.14-122.

DIMM Design Files

DEFINITION OF CU878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification

Registration - 200 pin DDR MiniDIMM. 0.60 mm Lead Centers. Item 11.14-069.

Registration - 200 pin Mini DIMM with 0.60 mm Lead Centers Socket Outline

Registration - Dual Inline Memory Module (DIMM) Family, 184 Pin DDR w/ 1.27 mm Contact Centers. Item 11.14-078

Standard - DDR3 DIMM Socket Insertion and Extraction Force Gauge. Item 11.14-098

STANDARD - FBDIMM Socket Insertion and Extraction Force Gauge. Item 11.14-083(S)

Registration - DDR2 SDRAM DIMM (Dual Inline memory Module) Family, Flex-Based, 1.00 mm Contact Centers.

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