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Title	Document #	Date
DDR5 SODIMM Raw Card Annex C Version 1	JESD309-S0-RCC	Jun 2022
This annex JESD309-S0-RCC, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Raw CardC Annex defines the design detail of x16, 1 Package Ranks DDR5 SODIMM. The common feature of DDR5 SODIMM such as the connector pinout can be found in the JESD309, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard. Committee(s): JC-45, JC-45.3 Free download. Registration or login required.
STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS:	JESD82-4B.01	Oct 2021
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision, shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required.
240-Pin Unbuffered and Registered DDR2 SDRAM DIMM Family	MODULE4.5.14	May 2021
Release No. 31This revision contains terminology updates only. Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184 Pin Unbuffered DDR SDRAM DIMM	MODULE4.5.10	May 2021
Release No.31This revision contains terminology updates only. Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184 Pin Unbuffered SDR SDRAM DIMM Family	MODULE4.5.11	May 2021
Release No.31This revision contains terminology updates only. Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification	MODULE4.20.19	May 2021
Release No. 31. Item 2131.03, 2078.04, 2131.06This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification	MODULE4.20.13	May 2021
Release 31. Item 2167.05This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
PC-2700/PC-3200 Registered DIMM Design Specification Revision 2.2	MODULE4.20.7	May 2021
Release 31. Item 2029.04This revision contains terminology updates only. Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - 288 Pin DDR4 DIMM, 0.85 mm Pitch. DIMM	MO-309F	Mar 2015
Item No. 11.14-176 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Dual Inline Memory Modules (DIMMs) Table of Contents	MODULE4.20.TOC	Dec 2014
Release No. 24 Committee(s): JC-42.2, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM) Family, 0.8 mm Pitch. DIMM	MO-274D	Oct 2014
Item 11.14-171 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 240 Pin DDR3 DIMM (Dual Inline Memory Module) Family with 1.00 mm pitch. DIM	MO-269J	Apr 2014
Item 11.14-163 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Standard Practices and Procedures - Module Insertion Procedure for DIMM and miniDIMM Connectors	SPP-023B	Feb 2013
Item 11.11-781(S) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM), 0.8 mm Pitch, Socket Outline.	SO-008B	Oct 2012
Item 11.14-141 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Annex N, R/C N, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2145.22	MODULE4.20.20.N	Sep 2012
Release No. 22. Item 2145.35 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - 244 Pin DDR2/DDR3 Mini Dual-In-Line Memory Module (DIMM) Family, 0.60 mm Lead Centers.	MO-244D	Jul 2012
Item No. 14-136 Patents(): Hitachi: 5,227,664 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification	MODULE4.20.20	Feb 2012
Release No. 22. Item 2082.94A Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex C, R/C C in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification	MODULE4.20.20.C	May 2011
Release No. 21 Item 2082.38A, 2082.71, 2100.02, 2100.04 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex AB, R/C AB in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification	MODULE4.20.20.AB	May 2011
Release No. 21 Item 2202.01 Committee(s): JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex J, R/C J in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification.	MODULE4.20.20.J	May 2011
Release No. 21 Item 2082.93 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - DDR2 SDRAM DIMM (Dual Inline Memory Module) Family with 1.00 mm Contact Centers.	MO-237-G.01	Apr 2011
Item 11.14-128, 11.14-128E Patents(): Hitachi: 5,227,664 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
240-Pin PC2-6400/PC2-5300/PC2-4200/PC2-3200 DDR2 SDRAM Registered DIMM Design Standard, Rev 4.04.	MODULE4.20.10	Jan 2010
Release No. 19A. Items 2133.37, 2191.00, 2191.02, 2129.12, 2113.33. Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex W, R/C W, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.07	MODULE4.20.20.W	Aug 2009
Release No. 19 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Annex Y, R/C Y, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.06	MODULE4.20.20.Y	Aug 2009
Release No. 19 Committee(s): JC-45.1, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Standard - SMT DDR3 DIMM Socket Coplanarity Measurement Gauge. Item 11.14-124.	GS-009A	Jan 2009
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR3 DIMM 240 Position Socket Outline, 1.00 mm Contact centers	SO-007B	Sep 2008
Item 11.14-119 Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
200-Pin DDR2 SDRAM Unbuffered SODIMM Design Specification	MODULE4.20.11	Jun 2008
Release No. 18. Item 2168.01 Committee(s): JC-45, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V	JESD8-18A	Mar 2008
This specification defines the high-speed differential point-to-point signaling link for FBDIMM, operating at the buffer supply voltage of 1.5V that is provided at the FBDIMM DIMM connector. This specification also applies to FBDIMM host chips which may operate with a different supply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit-stream. The first generation FBDIMM link is being specified to operate from 3.2 to 4.8 Gb/s. The specifications are defined for three distinct bit-rates of operation: 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-16 Free download. Registration or login required.
Registration - DDR3 SDRAM DIMM (Dual Inline Memory Module) Family, Flex-Based, 1.00 mm contact Centers	MO-290-A	Nov 2007
Item 11.14-118 Patents(): STAKTEK, See Outline Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR3 DIMM Connector Insertion Force Gauge. Item 11.14-110.	GS-008-A	Oct 2007
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 240 Pin DDR3 DIMM 1.00 mm Contact Centers, Press Fit Socket Outline.	SO-012A	Sep 2007
Item 11.14-112 Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 240 Pin DDR2 DIMM 1.00 mm Contact Centers, Press Fit Socket Outline. Item 11.14-111	SO-011A	Sep 2007
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - FBDIMM (Fully Buffered Dual Inline Memory Module) Family, 1.00 mm Contact Centers.	MO-256-F	Jun 2007
Item 11.14-108 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD	JEP152	May 2007
This document is the work product of the JC-45.1 DDR2 DIMM Clock Skew Measurement task group.The purpose of this document is to define procedures to measure clock parameters on registered DIMMs using the DDR2 Clock Reference Board. It is NOT the intent of this document to set specification values or validation requirements. Committee(s): JC-45, JC-45.1 Free download. Registration or login required.
DDR3 Unbuffered MicroDIMM Design Specification, 214-Pin PC3-12800. Item 2031.04	MODULE4.20.17	Mar 2007
Release No. 17 Committee(s): JC-45, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - DDR2 DIMM 240 Pin SMT Socket Outline with 1.00 mm Contact Centers. Item 11.14-097.	SO-009A	Feb 2007
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - FBDIMM (Dual In-Line Memory Module) Family, Flex-Based, 1.00 mm Contact Centers.	MO-282-A	Jan 2007
Item 11.14-099 Patents(): STAKTEK: See Outline Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-21	Jan 2007
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide a standard for a CUA845 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERS FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-18A	Jan 2007
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the CUA877 and CU2A877 PLL clock devices for registered DDR2 DIMM applications.The purpose is to provide a standard for the CUA877 and CU2A877 PLL clock devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
PC2-4200/PC2-3200 DDR2 Registered Mini-DIMM Design Specification Revision 2.0	MODULE4.20.14	Dec 2006
Release No. 16. Item 2105.00 Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers.	MO-260-C	Dec 2006
Item 11.14-101 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - DDR2 SDRAM DIMM (Dual Inline memory Module) Family, Flex-Based, 1.00 mm Contact Centers.	MO-281-A	Nov 2006
Item 11.14-100 Patents(): STAKTEK: See Outline Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 200 Pin DDR Small Outline Dual-In-Line Memory Module (SODIMM) Family, 0.60 mm Contact Centers. Item 11.14-077. Key tolerance corrected	MO-224-E	Nov 2006
Item 11-074(e) and 14-106(e) Patents(): Hatachi: 5,227,664 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD - FBDIMM Socket Insertion and Extraction Force Gauge. Item 11.14-083(S)	GS-004A	Oct 2006
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard - DDR3 DIMM Socket Insertion and Extraction Force Gauge. Item 11.14-098	GS-005A	Jul 2006
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Dual Inline Memory Module (DIMM) Family, 184 Pin DDR w/ 1.27 mm Contact Centers. Item 11.14-078	MO-206-E	Jan 2006
Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 200 pin Mini DIMM with 0.60 mm Lead Centers Socket Outline	SO-005A	Jan 2005
Item 11.14-070 Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 200 pin DDR MiniDIMM. 0.60 mm Lead Centers. Item 11.14-069.	MO-258-A	Dec 2004
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification	MODULE4.20.9	Nov 2004
Release No. 14 Committee(s): JC-42, JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DEFINITION OF CU878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-11	Sep 2004
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CU878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CU878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.3 Free download. Registration or login required.
DIMM Design Files	DIMM Homepage	Dec 2003
These reference files are registered as industry accepted examples for use by manufacturers. Please be sure to read the license agreement prior to downloading files. Design Files (Gerber Files) have been developed in accordance with the JEDEC Manual of Operation and Procedure. Committee(s): JC-42, JC-45 See DIMM Homepage information
Registration - 244 Pin DDR2/DDR3 Mini DIMM with 0.60 mm Lead Centers Socket Outline. Item 11.14-122.	SO-002B	Oct 2003
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Addition of 172 pin Micro DIMM variations and modification of terminal postional tolerance to Micro DIMM registration. Item 11.14-049.	MO-214-B	Sep 2002
0.50 mm Lead Centers Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION	JESD82-5	Jul 2002
This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently under development for DDR2 support devices. Committee(s): JC-40 Free download. Registration or login required.
200 Pin SDRAM DIMM	MODULE4.5.2	Oct 2001
Release No.11 Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin Registered SDRAM DIMM Family	MODULE4.5.7	Oct 2001
Release No.11 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:	JESD82-2	Jul 2001
This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module. Committee(s): JC-40 Free download. Registration or login required.
DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS:	JESD82	Jul 2000
This specification is a reference for Registered DDR DIMM designers. JESD82 defines the physical, electrical, interface and timing requirements of a 1:10 PLL clock driver for DDR Registered DIMMs from DDR200 to DDR266 as refined in revision C of JEDEC Standard 21-C (JESD21-C). JESD82 was also written to meet the future performance requirements of Registered DIMMs for DDR300 and DDR333. Committee(s): JC-40 Free download. Registration or login required.
168 Pin Unbuffered DRAM DIMM	MODULE4.5.3	Jun 1999
Release No. 9 Committee(s): JC-42 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
168 Pin DRAM DIMM	MODULE4.5.1	Mar 1999
Release No.9 Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.

Standards & Documents Search

DDR5 SODIMM Raw Card Annex C Version 1

STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS:

240-Pin Unbuffered and Registered DDR2 SDRAM DIMM Family

184 Pin Unbuffered DDR SDRAM DIMM

184 Pin Unbuffered SDR SDRAM DIMM Family

240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification

240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification

PC-2700/PC-3200 Registered DIMM Design Specification Revision 2.2

Registration - 288 Pin DDR4 DIMM, 0.85 mm Pitch. DIMM

Dual Inline Memory Modules (DIMMs) Table of Contents

Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM) Family, 0.8 mm Pitch. DIMM

Registration - 240 Pin DDR3 DIMM (Dual Inline Memory Module) Family with 1.00 mm pitch. DIM

Standard Practices and Procedures - Module Insertion Procedure for DIMM and miniDIMM Connectors

Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM), 0.8 mm Pitch, Socket Outline.

Annex N, R/C N, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2145.22

Registration - 244 Pin DDR2/DDR3 Mini Dual-In-Line Memory Module (DIMM) Family, 0.60 mm Lead Centers.

240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification

Annex C, R/C C in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification

Annex AB, R/C AB in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification

Annex J, R/C J in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Registered DIMM Design Specification.

Registration - DDR2 SDRAM DIMM (Dual Inline Memory Module) Family with 1.00 mm Contact Centers.

240-Pin PC2-6400/PC2-5300/PC2-4200/PC2-3200 DDR2 SDRAM Registered DIMM Design Standard, Rev 4.04.

Annex W, R/C W, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.07

Annex Y, R/C Y, in 240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800 DDR3 SDRAM Registered DIMM Design Specification. Item 2156.06

Standard - SMT DDR3 DIMM Socket Coplanarity Measurement Gauge. Item 11.14-124.

Registration - DDR3 DIMM 240 Position Socket Outline, 1.00 mm Contact centers

200-Pin DDR2 SDRAM Unbuffered SODIMM Design Specification

FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V

Registration - DDR3 SDRAM DIMM (Dual Inline Memory Module) Family, Flex-Based, 1.00 mm contact Centers

Registration - DDR3 DIMM Connector Insertion Force Gauge. Item 11.14-110.

Registration - 240 Pin DDR3 DIMM 1.00 mm Contact Centers, Press Fit Socket Outline.

Registration - 240 Pin DDR2 DIMM 1.00 mm Contact Centers, Press Fit Socket Outline. Item 11.14-111

Registration - FBDIMM (Fully Buffered Dual Inline Memory Module) Family, 1.00 mm Contact Centers.

DDR2 DIMM CLOCK SKEW MEASUREMENT PROCEDURE USING A CLOCK REFERENCE BOARD

DDR3 Unbuffered MicroDIMM Design Specification, 214-Pin PC3-12800. Item 2031.04

Registration - DDR2 DIMM 240 Pin SMT Socket Outline with 1.00 mm Contact Centers. Item 11.14-097.

Registration - FBDIMM (Dual In-Line Memory Module) Family, Flex-Based, 1.00 mm Contact Centers.

STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERS FOR REGISTERED DDR2 DIMM APPLICATIONS

PC2-4200/PC2-3200 DDR2 Registered Mini-DIMM Design Specification Revision 2.0

Registration - DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers.

Registration - DDR2 SDRAM DIMM (Dual Inline memory Module) Family, Flex-Based, 1.00 mm Contact Centers.

Registration - 200 Pin DDR Small Outline Dual-In-Line Memory Module (SODIMM) Family, 0.60 mm Contact Centers. Item 11.14-077. Key tolerance corrected

STANDARD - FBDIMM Socket Insertion and Extraction Force Gauge. Item 11.14-083(S)

Standard - DDR3 DIMM Socket Insertion and Extraction Force Gauge. Item 11.14-098

Registration - Dual Inline Memory Module (DIMM) Family, 184 Pin DDR w/ 1.27 mm Contact Centers. Item 11.14-078

Registration - 200 pin Mini DIMM with 0.60 mm Lead Centers Socket Outline

Registration - 200 pin DDR MiniDIMM. 0.60 mm Lead Centers. Item 11.14-069.

100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification

DEFINITION OF CU878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

DIMM Design Files

Registration - 244 Pin DDR2/DDR3 Mini DIMM with 0.60 mm Lead Centers Socket Outline. Item 11.14-122.

Registration - Addition of 172 pin Micro DIMM variations and modification of terminal postional tolerance to Micro DIMM registration. Item 11.14-049.

STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION

200 Pin SDRAM DIMM

168 Pin Registered SDRAM DIMM Family

STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:

DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS:

168 Pin Unbuffered DRAM DIMM

168 Pin DRAM DIMM

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