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Displaying 1 - 9 of 9 documents. Show 5 results per page.

Title	Document #	Date
DEFINITION OF CDCV857 PLL CLOCK DRIVER FOR REGISTERED DDR DIMM APPLICATIONS:	JESD82	Jul 2000
This specification is a reference for Registered DDR DIMM designers. JESD82 defines the physical, electrical, interface and timing requirements of a 1:10 PLL clock driver for DDR Registered DIMMs from DDR200 to DDR266 as refined in revision C of JEDEC Standard 21-C (JESD21-C). JESD82 was also written to meet the future performance requirements of Registered DIMMs for DDR300 and DDR333. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:	JESD82-2	Jul 2001
This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION	JESD82-5	Jul 2002
This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently under development for DDR2 support devices. Committee(s): JC-40 Free download. Registration or login required.
DEFINITION OF CU878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-11	Sep 2004
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CU878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CU878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40, JC-40.3 Free download. Registration or login required.
STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-21	Jan 2007
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide a standard for a CUA845 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERS FOR REGISTERED DDR2 DIMM APPLICATIONS	JESD82-18A	Jan 2007
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the CUA877 and CU2A877 PLL clock devices for registered DDR2 DIMM applications.The purpose is to provide a standard for the CUA877 and CU2A877 PLL clock devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V	JESD8-18A	Mar 2008
This specification defines the high-speed differential point-to-point signaling link for FBDIMM, operating at the buffer supply voltage of 1.5V that is provided at the FBDIMM DIMM connector. This specification also applies to FBDIMM host chips which may operate with a different supply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit-stream. The first generation FBDIMM link is being specified to operate from 3.2 to 4.8 Gb/s. The specifications are defined for three distinct bit-rates of operation: 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-16 Free download. Registration or login required.
STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS:	JESD82-4B.01	Oct 2021
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision, shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required.
DDR5 SODIMM Raw Card Annex C Version 1	JESD309-S0-RCC	Jun 2022
This annex JESD309-S0-RCC, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Raw CardC Annex defines the design detail of x16, 1 Package Ranks DDR5 SODIMM. The common feature of DDR5 SODIMM such as the connector pinout can be found in the JESD309, DDR5 Small Outline Dual Inline Memory Module (SODIMM) Common Standard. Committee(s): JC-45, JC-45.3 Free download. Registration or login required.