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The Load Reduced DIMM (LRDIMM) Memory Buffer (MB) supports DDR3 SDRAM main memory. The Memory Buffer allows buffering of memory traffic to support large memory capacities. Unlike DDR3 Register Buffer (SSTE32882), which only buffers Command, Address, Control and Clock, the LRDIMM Memory Buffer also buffers the Data (DQ) interface between the Memory Controller and the DRAM components. The Memory Buffer interface is responsible for memory requests to and from the local DIMM. LRDIMM provides a high memory bandwidth, large capacity channel solution for DDR3 main memory systems. LRDIMM uses commodity DRAMs isolated from the channel behind the Memory Buffer on the DIMM.

Committee(s): JC-40, JC-40.4

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Release No. 24;
Item 2114.44

Committee(s): JC-45, JC-45.3

JESD21-C Solid State Memory Documents Main Page

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Item 11.14-151

Patents(): Hatachi: 5,227,664

Committee(s): JC-11.14

JEP95 Registrations Main Page

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Release 23. Item 2114.28

Committee(s): JC-45, JC-45.3

JESD21-C Solid State Memory Documents Main Page

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