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Title	Document #	Date
DEFINITION OF THE SSTU32864 1.8 V CONFIGURABLE REGISTERED BUFFER FOR DDR2 RDIMM APPLICATIONS:	JESD82-7A.01	Feb 2023
Terminology update.This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTU32864 configurable registered buffer for DDR2 RDIMM applications. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS	JESD82-25.01	Jan 2023
Terminology update.This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32866 registered buffer with parity test for DDR2 RDIMM applications. Committee(s): JC-40 Free download. Registration or login required.
DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS	JESD82-26.01	Jan 2023
Terminology update. This standard defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUB32868 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
FBDIMM: ADVANCED MEMORY BUFFER (AMB)	JESDJESD82-20A.01	Jan 2023
This document is a core specification for a Fully Buffered DIMM (FBD) memory system. This document, along with the other core specifications, must be treated as a whole. Information critical to a Advanced Memory Buffer design appears in the other specifications, with specific cross-references provided. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-40 Free download. Registration or login required.
DEFINITION OF THE SSTU32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS	JESD82-10A.01	Oct 2021
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTU32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTU32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS	JESD82-16A.01	Oct 2021
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUA32866 registered buffer with parity test for DDR2 RDIMM applications. The purpose is to provide a standard for the SSTUA32866 (see Note) logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision as shown in Annex A of the document. Committee(s): JC-40, JC-40.3 Free download. Registration or login required.
DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS	JESD82-9B.01	Oct 2021
This standard provides the functional definition, ball-out configuration and package outline, signal definitions and input/output characteristics for a 28-bit 1:2 registered driver with parity suitable for use on DDR2 RDIMMs. The SSTU32865 integrates the functional equivalent of two SSTU32864 devices (as defined in JESD82-7) into a single device, thereby easing layout and board design constraints especially on high density RDIMMs such as dual rank, by four configurations. Moreover, the optional use of a parity function is provided for, permitting detection and reporting of parity errors across its 22 data inputs. JESD82-9 specifies a 160-pin Thin-profile, fine-pitch ball-grid array (TFBGA) package. This is a minor editorial revision as shown in Annex A of the document. Committee(s): JC-40, JC-40.4 Free download. Registration or login required.
DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS	JESD82-14A.01	Oct 2021
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTUB32868 registered buffer with parity test for DDR2 RDIMM applications. SSTU32S2868 denotes a single-die implementation and SSTU32D868 denotes a dual-die implementation. This is a minor editorial revision as shown in Annex A of the document. Committee(s): JC-40 Free download. Registration or login required.
240-Pin Unbuffered and Registered DDR2 SDRAM DIMM Family	MODULE4.5.14	May 2021
Release No. 31This revision contains terminology updates only. Committee(s): JC-42, JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification	MODULE4.20.13	May 2021
Release 31. Item 2167.05This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM), 0.8 mm Pitch, Socket Outline.	SO-008B	Oct 2012
Item 11.14-141 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 244 Pin DDR2/DDR3 Mini Dual-In-Line Memory Module (DIMM) Family, 0.60 mm Lead Centers.	MO-244D	Jul 2012
Item No. 14-136 Patents(): Hitachi: 5,227,664 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
240-Pin PC2-6400/PC2-5300/PC2-4200/PC2-3200 DDR2 SDRAM Registered DIMM Design Standard, Rev 4.04.	MODULE4.20.10	Jan 2010
Release No. 19A. Items 2133.37, 2191.00, 2191.02, 2129.12, 2113.33. Committee(s): JC-45, JC-45.1 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
DDR2 SDRAM STANDARD	JESD79-2F	Nov 2009
This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01 Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
DDR2 Specific SDRAM Function	SDRAM3.11.5.5	Jul 2008
Release No. 18 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
200-Pin DDR2 SDRAM Unbuffered SODIMM Design Specification	MODULE4.20.11	Jun 2008
Release No. 18. Item 2168.01 Committee(s): JC-45, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V	JESD8-18A	Mar 2008
This specification defines the high-speed differential point-to-point signaling link for FBDIMM, operating at the buffer supply voltage of 1.5V that is provided at the FBDIMM DIMM connector. This specification also applies to FBDIMM host chips which may operate with a different supply voltage. The link consists of a transmitter and a receiver and the interconnect in between them. The transmitter sends serialized bits into a lane and the receiver accepts the electrical signals of the serialized bits and transforms them into a serialized bit-stream. The first generation FBDIMM link is being specified to operate from 3.2 to 4.8 Gb/s. The specifications are defined for three distinct bit-rates of operation: 3.2 Gb/s, 4.0 Gb/s and 4.8 Gb/s. Patents(): There are known patent issues that are common to all FBDIMM related specifications. See document for link to FBDIMM Patents. Committee(s): JC-16 Free download. Registration or login required.
SPECIALITY DDR2-1066 SDRAM	JESD208	Nov 2007
This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices. Committee(s): JC-42.3 Free download. Registration or login required.
Registration - 240 Pin DDR2 DIMM 1.00 mm Contact Centers, Press Fit Socket Outline. Item 11.14-111	SO-011A	Sep 2007
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Standard - DDR2 DIMM Socket Insertion and Extraction Force Gauge. Item 11.14-103.	GS-007-A	Jun 2007
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.

Standards & Documents Search

DEFINITION OF THE SSTU32864 1.8 V CONFIGURABLE REGISTERED BUFFER FOR DDR2 RDIMM APPLICATIONS:

DEFINITION OF the SSTUB32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

DEFINITION OF THE SSTUB32868 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS

FBDIMM: ADVANCED MEMORY BUFFER (AMB)

DEFINITION OF THE SSTU32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

DEFINITION OF THE SSTUA32866 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY TEST FOR DDR2 RDIMM APPLICATIONS

DEFINITION OF SSTU32865 REGISTERED BUFFER WITH PARITY FOR 2R x 4 DDR2 RDIMM APPLICATIONS

DEFINITION OF THE SSTUB32868 1.8 V CONFIGURABLE REGISTERED BUFFER WITH PARITY FOR DDR2 RDIMM APPLICATIONS

240-Pin Unbuffered and Registered DDR2 SDRAM DIMM Family

240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification

Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM), 0.8 mm Pitch, Socket Outline.

Registration - 244 Pin DDR2/DDR3 Mini Dual-In-Line Memory Module (DIMM) Family, 0.60 mm Lead Centers.

240-Pin PC2-6400/PC2-5300/PC2-4200/PC2-3200 DDR2 SDRAM Registered DIMM Design Standard, Rev 4.04.

DDR2 SDRAM STANDARD

DDR2 Specific SDRAM Function

200-Pin DDR2 SDRAM Unbuffered SODIMM Design Specification

FBDIMM SPECIFICATION: HIGH SPEED DIFFERENTIAL PTP LINK AT 1.5 V

SPECIALITY DDR2-1066 SDRAM

Registration - 240 Pin DDR2 DIMM 1.00 mm Contact Centers, Press Fit Socket Outline. Item 11.14-111

Standard - DDR2 DIMM Socket Insertion and Extraction Force Gauge. Item 11.14-103.

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