Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # |
Date![]() |
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144 Pin DDR SGRAM SO-DIMM |
MODULE4.5.9 | Mar 1999 |
Release No. 9 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH: |
JESD73-4 | Nov 2001 |
This standard provides a set of uniform data sheet parameters for the description of a dual 5-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay. Free download. Registration or login required. |
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STANDARD FOR DESCRIPTION OF 3867 - 2.5 V, SINGLE 10-BIT, 2-PORT, DDR FET SWITCH: |
JESD73-3 | Nov 2001 |
This standard provides a set of uniform data sheet parameters for the description of a single 10-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay. Free download. Registration or login required. |
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DDR Specific SDRAM Functions |
SDRAM3.11.5.2 | Jun 2003 |
Release No. 13 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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200 Pin, PC-2700/PC-2100/PC-1600 Unbuffered SO-DIMM SDRAM Reference Design Specification |
MODULE4.20.6 | Oct 2003 |
Release No. 13 Committee(s): JC-42.5 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DIMM Design Files |
DIMM Homepage | Dec 2003 |
These reference files are registered as industry accepted examples for use by manufacturers. Please be sure to read the license agreement prior to downloading files. Design Files (Gerber Files) have been developed in accordance with the JEDEC Manual of Operation and Procedure. |
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SPD Annex D, DDR Synchronous DRAM (DDR SDRAM) |
SPD4.1.2.4 | Jan 2004 |
Release No.13 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DEFINITION OF CVF857 PLL CLOCK DRIVER FOR REGISTERED PC1600, PC2100, PC2700, AND PC3200 DIMM APPLICATIONS: |
JESD82-1A | May 2004 |
This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CV857 PLL clock device for registered PC1600, PC2100, PC2700 and PC3200 DIMM applications. The purpose is to provide a standard for a CV857 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required. |
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100-Pin DDR SDRAM Unbuffered 32b-DIMM Design Specification |
MODULE4.20.9 | Nov 2004 |
Release No. 14 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DRIVER SPECIFICATIONS FOR 1.8 V POWER SUPPLY POINT-TO-POINT DRIVERS |
JESD8-17 | Nov 2004 |
This material is intended to be reflected in supplier specifications for point to point DDR devices ranging from 400 Mb/s to 800 Mb/s operation. It is a method to specify driver impedance with something other than a number that does not nec-essarily define how it operates in a real net This standard addresses this issue using net lengths and specifies how much uncertainty can exist in the data for each speed supported. Free download. Registration or login required. |
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Registration - 200 pin DDR MiniDIMM. 0.60 mm Lead Centers. Item 11.14-069. |
MO-258-A | Dec 2004 |
Free download. Registration or login required. |
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Registration - Connector Outline for DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers. Item 11.14-076. |
SO-004A | May 2005 |
Free download. Registration or login required. |
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Registration - Dual Inline Memory Module (DIMM) Family, 184 Pin DDR w/ 1.27 mm Contact Centers. Item 11.14-078 |
MO-206-E | Jan 2006 |
Committee(s): JC-11.14 Free download. Registration or login required. |
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Registration - 200 Pin DDR Small Outline Dual-In-Line Memory Module (SODIMM) Family, 0.60 mm Contact Centers. Item 11.14-077. Key tolerance corrected |
MO-224-E | Nov 2006 |
Item 11-074(e) and 14-106(e) Patents(): Hatachi: 5,227,664 Committee(s): JC-11.14 Free download. Registration or login required. |
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Registration - DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers. |
MO-260-C | Dec 2006 |
Item 11.14-101 Free download. Registration or login required. |
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High Speed DDR SRAM in 165 BGA |
SRAM3.7.10 | Feb 2008 |
Release No. 17. Item 1755 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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DDR2 Specific SDRAM Function |
SDRAM3.11.5.5 | Jul 2008 |
Release No. 18 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O. |
JESD209A-1 | Mar 2009 |
This document defines the Low Power Double Data Rate (LPDDR) SDRAM 1.2 V I/O, including AC and DC operating conditions, extended mode register settings, and I-V characteristics. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 2 Gb for x16 and x32 Low Power Double Data Rate SDRAM devices with 1.2 V I/O. System designs based on the required aspects of this specification will be supported by all LPDDR SDRAM vendors providing compliant devices. Committee(s): JC-42.6 Free download. Registration or login required. |
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EMBEDDED MULTIMEDIACARD(e·MMC) e·MMC/CARD PRODUCT STANDARD, HIGH CAPACITY, Including Reliable Write, Boot, Sleep Modes, Dual Data Rate, Multiple Partitions Supports and Security Enhancement (MMCA, 4.4) - SUPERSEDED BY JESD84-A441, March 2010Status: Superseded April 2010 |
JESD84-A44 | Mar 2009 |
Committee(s): JC-64 Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD |
JESD209B | Feb 2010 |
This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other higher density devices. The purpose of this document is to define the minimum set of requirements for JEDEC compliant 64Mb through 2Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects of this standard will be supported by all LPDDR SDRAM vendors providing compliant devices. (JESD209 was originally numbered as JESD79-4 May 2006 to August 2007, corrected to JESD209 09/17/2007). Patents(): See Document Committee(s): JC-42.3, JC-42.6 Free download. Registration or login required. |