Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
NAND Flash Interface Interoperability |
JESD230F.01 | May 2023 |
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Committee(s): JC-42.4 Free download. Registration or login required. |
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Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFSRelease Number: 32 |
MCP3.12.1 | Mar 2023 |
Item 140.07B. This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.
Committee(s): JC-64.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.19 | May 2021 |
Release No. 31. Item 2131.03, 2078.04, 2131.06 This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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184 Pin Unbuffered DDR SDRAM DIMM |
MODULE4.5.10 | May 2021 |
Release No.31 This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.13 | May 2021 |
Release 31. Item 2167.05 This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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