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Title	Document #	Date
NAND Flash Interface Interoperability	JESD230F.01	May 2023
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Committee(s): JC-42.4 Free download. Registration or login required.
Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFS Release Number: 32	MCP3.12.1	Mar 2023
Item 140.07B. This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution. Committee(s): JC-64.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification	MODULE4.20.19	May 2021
Release No. 31. Item 2131.03, 2078.04, 2131.06 This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
184 Pin Unbuffered DDR SDRAM DIMM	MODULE4.5.10	May 2021
Release No.31 This revision contains terminology updates only. Committee(s): JC-42, JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification	MODULE4.20.13	May 2021
Release 31. Item 2167.05 This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM) Family, 0.8 mm Pitch. DIMM	MO-274D	Oct 2014
Item 11.14-171 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules, Release 6	SPD4.1.2.11	Feb 2014
Release No. 24. Item 2065.47A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM), 0.8 mm Pitch, Socket Outline.	SO-008B	Oct 2012
Item 11.14-141 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
DDR3 SDRAM STANDARD	JESD79-3F	Jul 2012
This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14 Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3 Available for purchase: $247.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
Registration - DDR2 SDRAM DIMM (Dual Inline Memory Module) Family with 1.00 mm Contact Centers.	MO-237-G.01	Apr 2011
Item 11.14-128, 11.14-128E Patents(): Hitachi: 5,227,664 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD	JESD209B	Feb 2010
This standard defines the Low Power Double Data Rate (LPDDR) SDRAM, including features, functionality, AC and DC characteristics, packages, and pin assignments. This scope may be expanded in future to also include other higher density devices. The purpose of this document is to define the minimum set of requirements for JEDEC compliant 64Mb through 2Gb for x16 and x32 Low Power Double Data Rate SDRAM devices. System designs based on the required aspects of this standard will be supported by all LPDDR SDRAM vendors providing compliant devices. (JESD209 was originally numbered as JESD79-4 May 2006 to August 2007, corrected to JESD209 09/17/2007). Patents(): See Document Committee(s): JC-42.3, JC-42.6 Free download. Registration or login required.
EMBEDDED MULTIMEDIACARD(e·MMC) e·MMC/CARD PRODUCT STANDARD, HIGH CAPACITY, Including Reliable Write, Boot, Sleep Modes, Dual Data Rate, Multiple Partitions Supports and Security Enhancement (MMCA, 4.4) - SUPERSEDED BY JESD84-A441, March 2010 Status: Superseded April 2010	JESD84-A44	Mar 2009
Committee(s): JC-64 Free download. Registration or login required.
Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O.	JESD209A-1	Mar 2009
This document defines the Low Power Double Data Rate (LPDDR) SDRAM 1.2 V I/O, including AC and DC operating conditions, extended mode register settings, and I-V characteristics. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 2 Gb for x16 and x32 Low Power Double Data Rate SDRAM devices with 1.2 V I/O. System designs based on the required aspects of this specification will be supported by all LPDDR SDRAM vendors providing compliant devices. Committee(s): JC-42.6 Free download. Registration or login required.
DDR2 Specific SDRAM Function	SDRAM3.11.5.5	Jul 2008
Release No. 18 Committee(s): JC-42.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
High Speed DDR SRAM in 165 BGA	SRAM3.7.10	Feb 2008
Release No. 17. Item 1755 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers.	MO-260-C	Dec 2006
Item 11.14-101 Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 200 Pin DDR Small Outline Dual-In-Line Memory Module (SODIMM) Family, 0.60 mm Contact Centers. Item 11.14-077. Key tolerance corrected	MO-224-E	Nov 2006
Item 11-074(e) and 14-106(e) Patents(): Hatachi: 5,227,664 Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Dual Inline Memory Module (DIMM) Family, 184 Pin DDR w/ 1.27 mm Contact Centers. Item 11.14-078	MO-206-E	Jan 2006
Committee(s): JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Connector Outline for DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers. Item 11.14-076.	SO-004A	May 2005
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - 200 pin DDR MiniDIMM. 0.60 mm Lead Centers. Item 11.14-069.	MO-258-A	Dec 2004
Committee(s): JC-11, JC-11.14 JEP95 Registrations Main Page Free download. Registration or login required.

Standards & Documents Search

NAND Flash Interface Interoperability

Multichip Packages (MCP) and Discrete e•MMC, e•2MMC, and UFS

240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification

184 Pin Unbuffered DDR SDRAM DIMM

240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification

Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM) Family, 0.8 mm Pitch. DIMM

SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules, Release 6

Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM), 0.8 mm Pitch, Socket Outline.

DDR3 SDRAM STANDARD

Registration - DDR2 SDRAM DIMM (Dual Inline Memory Module) Family with 1.00 mm Contact Centers.

LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM STANDARD

EMBEDDED MULTIMEDIACARD(e·MMC) e·MMC/CARD PRODUCT STANDARD, HIGH CAPACITY, Including Reliable Write, Boot, Sleep Modes, Dual Data Rate, Multiple Partitions Supports and Security Enhancement (MMCA, 4.4) - SUPERSEDED BY JESD84-A441, March 2010

Addendum No. 1 to JESD209A, LOW POWER DOUBLE DATA RATE (LPDDR) SDRAM, 1.2 V I/O.

DDR2 Specific SDRAM Function

High Speed DDR SRAM in 165 BGA

Registration - DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers.

Registration - 200 Pin DDR Small Outline Dual-In-Line Memory Module (SODIMM) Family, 0.60 mm Contact Centers. Item 11.14-077. Key tolerance corrected

Registration - Dual Inline Memory Module (DIMM) Family, 184 Pin DDR w/ 1.27 mm Contact Centers. Item 11.14-078

Registration - Connector Outline for DDR and DDR2 Micro DIMM Mezzanine, 214 pin, 0.4 mm Lead Centers. Item 11.14-076.

Registration - 200 pin DDR MiniDIMM. 0.60 mm Lead Centers. Item 11.14-069.

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