Global Standards for the Microelectronics Industry
Standards & Documents Search
Title | Document # | Date |
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Registration - DDR2 SDRAM DIMM (Dual Inline Memory Module) Family with 1.00 mm Contact Centers. |
MO-237-G.01 | Apr 2011 |
Item 11.14-128, 11.14-128E Patents(): Hitachi: 5,227,664 Committee(s): JC-11.14 Free download. Registration or login required. |
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DDR3 SDRAM STANDARD |
JESD79-3F | Jul 2012 |
This document defines the DDR3 SDRAM standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 512 Mb through 8 Gb for x4, x8, and x16 DDR3 SDRAM devices. This document was created based on the DDR2 standard (JESD79-2) and some aspects of the DDR standard (JESD79). Each aspect of the changes for DDR3 SDRAM operation were considered and approved by committee ballots). The accumulation of these ballots were then incorporated to prepare this standard (JESD79-3), replacing whole sections and incorporating the changes into Functional Description and Operation. Item 1627.14 Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office. Committee(s): JC-42.3 Available for purchase: $247.00 Add to Cart Paying JEDEC Members may login for free access. |
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Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM), 0.8 mm Pitch, Socket Outline. |
SO-008B | Oct 2012 |
Item 11.14-141 Free download. Registration or login required. |
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SPD Annex K - Serial Presence Detect (SPD) for DDR3 SDRAM Modules, Release 6 |
SPD4.1.2.11 | Feb 2014 |
Release No. 24. Item 2065.47A Committee(s): JC-45 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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Registration - DDR1/DDR2/DDR3, 144 Pin, 16b/32b Small Outline Dual Inline Memory Module (SODIMM) Family, 0.8 mm Pitch. DIMM |
MO-274D | Oct 2014 |
Item 11.14-171 Free download. Registration or login required. |
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240-Pin PC2-5300/PC2-6400 DDR2 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.13 | May 2021 |
Release 31. Item 2167.05 This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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240-Pin PC3-6400/PC3-8500/PC3-10600/PC3-12800/PC3-14900/PC3-17000 DDR3 SDRAM Unbuffered DIMM Design Specification |
MODULE4.20.19 | May 2021 |
Release No. 31. Item 2131.03, 2078.04, 2131.06 This revision contains terminology updates only. Committee(s): JC-45, JC-45.2, JC-45.3 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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184 Pin Unbuffered DDR SDRAM DIMM |
MODULE4.5.10 | May 2021 |
Release No.31 This revision contains terminology updates only. JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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MCP and Discrete e•MMC, e•2MMC, and UFSRelease Number: 33 |
MCP3.12.1-1 | Jun 2024 |
Item 142.12 This section provides electrical interface items related to Multi-Chip Packages (MCP) and Stacked-Chip Scale Packages (SCSP) of mixed memory technologies including Flash (NOR and NAND), SRAM, PSRAM, LPDRAM, USF, etc. These items include die-on-die stacking within a single encapsulated package, package-on-package or module-in-package technologies, etc. The Section also contains Silicon Pad Sequence information for the various memory technologies to aid in the design and electrical optimization of the memory sub-system or complete memory stacked solution.
Committee(s): JC-64.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required. |
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NAND Flash Interface Interoperability |
JESD230G | Oct 2024 |
This standard was jointly developed by JEDEC and the Open NAND Flash Interface Workgroup, hereafter referred to as ONFI. This standard defines a standard NAND flash device interface interoperability standard that provides means for system be designed that can support Asynchronous SDR, Synchronous DDR and Toggle DDR NAND flash devices that are interoperable between JEDEC and ONFI member implementations. Free download. Registration or login required. |
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