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Title	Document #	Date
BALL GRID ARRAY PINOUT FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS:	JESD75-4	Mar 2004
This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to DSBGA-packaged 1-, 2- and 3-bit logic devices. Committee(s): JC-40 Free download. Registration or login required.
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE:	JESD75-1	Oct 2001
This standard establishes a 54 Ball Grid Array pinout for 16, 18 and 20-bit standard logic devices that are currently being produced in 48 and 56 Pin SSOP and TSSOP packages. The 54 Ball Grid Array Package is organized as a 6 x 9 array with balls on a .8mm x .8mm grid pitch. Committee(s): JC-40 Free download. Registration or login required.
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16-BIT LOGIC FUNCTIONS:	JESD75-2	Jul 2001
This standard provides a pinout standard for 16-bit wide logic devices offered in a 56-ball areagrid array package to provide for uniformity, multiplicity of sources, elimination of confusion,ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONS:	JESD75-3	Jul 2001
This standard provides a pinout standard for 8-bit logic devices offered in a 20-ball area gridarray package to provide for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. Committee(s): JC-40 Free download. Registration or login required.
Design Requirements - Ball Grid Array (BGA)Package Measuring and Methodology.	DG-4.17C	Jul 2008
Item 11.2-791(S) Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Ball Grid Array Package (BGA)	DR-4.14J.01	Feb 2019
Item 11.2-948E Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Ball Grid Array Package (BGA) and Interstitial Ball Grid Array Package (IBGA)	DR-4.5N.01	Nov 2018
Ball Pitch = 0.40, 0.50, 0.65, 0.75 and 0.80 mm. Body sizes = ≤ 21 mm.Item 11.2-968E, Editorial Change. Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Die-Size Ball Grid Array Packages (DSBGA) Design Guide.	DG-4.7F	Jan 2014
Item 11.2-829R Committee(s): JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Fine-pitch, Square Ball Grid Array Package (FBGA) Package-on-Package (PoP).	DR-4.22C.02	Mar 2011
Item 11.2-839(R) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
Design Requirements - Wafer Level Ball Grid Arrays (WLBGA).	DR-4.18A.01	Apr 2021
Item 11.2-965(E) Committee(s): JC-11, JC-11.2 JEP95 Registrations Main Page Free download. Registration or login required.
EMBEDDED MULTIMEDIACARD (e·MMC) MECHANICAL STANDARD	JESD84-C43	Dec 2007
This document is a mechanical product specification for a high capacity embedded memory device using the MMC interface version 4.2 and a BGA package Committee(s): JC-64, JC-64.2 Free download. Registration or login required.
High Speed DDR SRAM in 165 BGA	SRAM3.7.10	Feb 2008
Release No. 17. Item 1755 Committee(s): JC-42, JC-42.2 JESD21-C Solid State Memory Documents Main Page Free download. Registration or login required.
Registration - Ball Grid Array Family, Rectangular, 1.0 mm pitch. (V, T, L) R-PBGA	MO-304D	Jul 2013
Item 11.11-882 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Ball Grid Array Family, Rectangular, 1.00 mm Pitch. PBGA.	MO-234E	Jun 2018
Item 11.11-954 Patents(): National Semiconductor: 4688152; 4778641; 4868349. Citizen Watch Company: 4822550; 4935581. Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Die Size Ball Grid Array, Fine Pitch, Thin/Very Thin/Extremely Thin Profile. X-DSBGA. Item 11.4-631.	MO-211-C	Jun 2004
Committee(s): JC-11.4 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Dual-Pitch, rectangular Ball Grid Array package, 0.50 mm x 0.65 mm Pitch. LFR-XBGA	MO-307A	Dec 2011
Item 11.11-856 Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Extremely Thin, Two Row Cavity Down, 0.50 mm Pitch BGA Family. The addition of -2, max matrix, variations to XFBGA. Item 11.11-604.	MO-221-C	Jun 2001
Committee(s): JC-11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Low Profile Square Ball Grid Array Family. S-LBGA-B/LBGA.	MO-192-F	Jul 2003
Item 11.11-659 Patents(): National Semiconductor, Citizen Watch Company: See Outline Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Low profile, Fine Pitch Ball Grid Array Family, Square. LF-XBGA. Item 11.11-751E.	MO-275-A.01	Jul 2011
Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.
Registration - Low Profile, Fine Pitch BGA Family, 0.80 mm Pitch (Rectangular). LFR-XBGA. Item 11.11-752.	MO-205-G	Jul 2006
Committee(s): JC-11, JC-11.11 JEP95 Registrations Main Page Free download. Registration or login required.

Standards & Documents Search

BALL GRID ARRAY PINOUT FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS:

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16, 18, AND 20-BIT LOGIC FUNCTIONS USING A 54 BALL PACKAGE:

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 16-BIT LOGIC FUNCTIONS:

BALL GRID ARRAY PINOUTS STANDARDIZED FOR 8-BIT LOGIC FUNCTIONS:

Design Requirements - Ball Grid Array (BGA)Package Measuring and Methodology.

Design Requirements - Ball Grid Array Package (BGA)

Design Requirements - Ball Grid Array Package (BGA) and Interstitial Ball Grid Array Package (IBGA)

Design Requirements - Die-Size Ball Grid Array Packages (DSBGA) Design Guide.

Design Requirements - Fine-pitch, Square Ball Grid Array Package (FBGA) Package-on-Package (PoP).

Design Requirements - Wafer Level Ball Grid Arrays (WLBGA).

EMBEDDED MULTIMEDIACARD (e·MMC) MECHANICAL STANDARD

High Speed DDR SRAM in 165 BGA

Registration - Ball Grid Array Family, Rectangular, 1.0 mm pitch. (V, T, L) R-PBGA

Registration - Ball Grid Array Family, Rectangular, 1.00 mm Pitch. PBGA.

Registration - Die Size Ball Grid Array, Fine Pitch, Thin/Very Thin/Extremely Thin Profile. X-DSBGA. Item 11.4-631.

Registration - Dual-Pitch, rectangular Ball Grid Array package, 0.50 mm x 0.65 mm Pitch. LFR-XBGA

Registration - Extremely Thin, Two Row Cavity Down, 0.50 mm Pitch BGA Family. The addition of -2, max matrix, variations to XFBGA. Item 11.11-604.

Registration - Low Profile Square Ball Grid Array Family. S-LBGA-B/LBGA.

Registration - Low profile, Fine Pitch Ball Grid Array Family, Square. LF-XBGA. Item 11.11-751E.

Registration - Low Profile, Fine Pitch BGA Family, 0.80 mm Pitch (Rectangular). LFR-XBGA. Item 11.11-752.

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