Global Standards for the Microelectronics Industry
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Displaying 1 - 5 of 7 documents. Show 5 results per page.
Title | Document # |
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CLASSIFICATION OF NON-IC ELECTRONIC COMPONENTS FOR ASSEMBLY PROCESSES |
J-STD-075A | May 2018 |
This is a Joint Standard between ECIA, IPC, and JEDEC. The purpose of this standard is to establish an agreed set of worst case solder process limits (SnPb and Pb-free) which can safely be used for assembling non-semiconductor electronic components on common substrates, e.g., FR4, ceramic, polyimide, etc., along with documenting unique commodity specific exceptions. The documented process conditions are used to evaluate a non-semiconductor component’s PSL and MSL. THIS DOCUMENT IS NOT AVAILABLE FOR FREE DOWNLOAD. However, this document is available to the JEDEC formulating Committee members, in the Members Area. The lead organization is ECIA. Committee(s): JC-14 |
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JOINT IPC/JEDEC STANDARD FOR HANDLING, PACKING, SHIPPING, AND USE OF MOISTURE/REFLOW SENSITIVE SURFACE-MOUNT DEVICES |
J-STD-033D | Apr 2018 |
The purpose of this document is to provide manufacturers and users with standardized methods for handling, packing, shipping, and use of moisture/reflow and process sensitive devices that have been classified to the levels defined in J-STD-020 or J-STD-075. These methods are provided to avoid damage from moisture absorption and exposure to solder reflow temperatures that can result in yield and reliability degradation. By using these procedures, safe and damage-free reflow can be achieved. The dry-packing process defined herein provides a minimum shelf life of 12 months from the seal date. Free download. Registration or login required. |
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CUSTOMER NOTIFICATION STANDARD FOR PRODUCT/PROCESS CHANGES BY ELECTRONIC PRODUCT SUPPLIERS |
J-STD-046 | Jul 2016 |
This standard is applicable to suppliers of, and affected customers for, electronic products and their constituent components. This standard establishes the requirements for timely customer notification of changes to electronic products and associated processes. This document replaces JESD46. Committee(s): JC-14.4 Free download. Registration or login required. |
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MARKING, SYMBOLS, AND LABELS OF LEADED AND LEAD-FREE TERMINAL FINISHED MATERIALS USED IN ELECTRONIC ASSEMBLY |
J-STD-609B | Apr 2016 |
This standard applies to components and assemblies that contain Pb-free and Pb-containing solders and finishes. This standard describes the marking of components and the labeling of their shipping containers to identify their 2nd level terminal finish or material, and applies to components that are intended to be attached to boards or assemblies with solder or mechanical clamping or are press fit. This standard also applies to 2nd level terminal materials for bumped die that are used for direct board attach. Free download. Registration or login required. |
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JOINT IPC/JEDEC STANDARD FOR MOISTURE/REFLOW SENSITIVITY CLASSIFICATION FOR NONHERMETIC SURFACE-MOUNT DEVICES |
J-STD-020E | Dec 2014 |
This document identifies the classification level of nonhermetic solid-state surface mount devices (SMDs) that are sensitive to moisture-induced stress. It is used to determine what classification level should be used for initial reliability qualification. Once identified, the SMDs can be properly packaged, stored and handled to avoid subsequent thermal and mechanical damage during the assembly solder reflow attachment and/or repair operation. This revision now covers components to be processed at higher temperatures for lead-free assembly. Free download. Registration or login required. |