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Title	Document #	Date
ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements Schema	JEP181_Schema_R2p0	Nov 2023
In conjunction with JEP181A, for user support this file is the entire “XML Requirements Schema”. Committee(s): JC-15 Free download. Registration or login required.
Guideline for Evaluating Bipolar Degradation of Silicon Carbide Power Devices	JEP197	Nov 2023
This publication provides guidance to SiC product suppliers and related power electronic industries in their evaluation of bipolar degradation mechanism in SiC power devices. Committee(s): JC-70, JC-70.2 Free download. Registration or login required.
Guideline for Reverse Bias Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices	JEP198	Nov 2023
This publication presents guidelines for evaluating the Time Dependent Breakdown (TDB) reliability of GaN power switches. Committee(s): JC-70, JC-70.1 Free download. Registration or login required.
JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES	JEP166E	Jul 2023
This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories Committee(s): JC-42.6 Free download. Registration or login required.
GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTS Status: Reaffirmed May 2023	JEP142	May 2023
This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests. Committee(s): JC-13, JC-13.5 Free download. Registration or login required.
Guidelines for Particle Impact Noise Detection (PIND) Testing, Operator Training, and Certification	JEP114A	May 2023
This publication is a guideline to test facilities in their efforts to establish and maintain consistent particle impact noise detection (PIND) testing. Committee(s): JC-13, JC-13.5 Free download. Registration or login required.
Guidelines for Supplier Performance Rating	JEP146B	May 2023
This publication establishes guidelines and provides examples by which customers can measure their suppliers based on mutually agreed upon objective criteria. Committee(s): JC-14, JC-14.4 Free download. Registration or login required.
Guidelines for Packing and Labeling of Integrated Circuits in Unit Container Packing (Tubes, Trays, and Tape and Reel)	JEP130C	Feb 2023
This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality. Committee(s): JC-14, JC-14.4 Free download. Registration or login required.
Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices for Power Electronic Conversion	JEP195	Feb 2023
This document elaborates on the information given in JEP184 regarding the long-time stability of device parameters under static conditions and under application near switching conditions. Committee(s): JC-70, JC-70.2 Free download. Registration or login required.
Guideline for Gate Oxide Reliability and Robustness Evaluation Procedures for Silicon Carbide Power MOSFETs	JEP194	Feb 2023
This document provides guidelines for evaluating gate reliability and lifetime testing for silicon carbide (SiC) based power devices with a gate oxide or gate dielectric. Committee(s): JC-70, JC-70.2 Free download. Registration or login required.
Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs	JEP183A	Jan 2023
This publication describes the guidelines for VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. Committee(s): JC-70.1 Free download. Registration or login required.
Guidelines for Gate Charge (QG) Test Method for SiC MOSFET	JEP192	Jan 2023
This publication defines a QGS, TOT, QGD and QGS, TH which can be extracted from a measured QG waveform for SiC MOSFETs. Committee(s): JC-70, JC-70.2 Free download. Registration or login required.
SELECTION OF BURN-IN / LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS	JEP163A	Jan 2023
This publication is a guideline to assist manufacturers of integrated circuits in defining conditions for burn-in and life test of their products to meet quality and reliability performance requirements of MIL-PRF-38535. Committee(s): JC-13, JC-13.2 Free download. Registration or login required.
Survey On Latch-Up Testing Practices and Recommendations for Improvements	JEP193	Jan 2023
This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
PROCESS CHARACTERIZATION GUIDELINE	JEP132A.01	Dec 2022
This guideline provides a methodology to characterize a new or existing process and is applicable to any manufacturing or service process. It describes when to use specific tools such as failure mode effects analysis (FEMA), design or experiments (DOE), measurement system evaluation (MSE), capability analysis (CpK), statistical process control (SPC), and problem solving tools. It also provides a brief description of each tool. Committee(s): JC-13 Free download. Registration or login required.
SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED)	JEP164	Oct 2022
This white paper presents the recent knowledge of system ESD field events and air discharge testing methods. Testing experience with the IEC 61000-4-2 (2008) and the ISO 10605 ESD standards has shown a range of differing interpretations of the test method and its scope. This often results in misapplication of the test method and a high test result uncertainty. This white paper aims to explain the problems observed and to suggest improvements to the ESD test standard and to enable a correlation with a SEED IC/PCB co-design methodology. Committee(s): JC-14.3 Free download. Registration or login required.
Guideline for Evaluating dv/dt Robustness of SiC Power Devices, Version 1.0	JEP190	Aug 2022
This document provides stress procedures, general failure criteria and documentation guidelines such that the dv/dt robustness can be demonstrated, evaluated and documented. This document gives examples for test setups which can be used and the corresponding test conditions. Additionally, criteria are explained under which device manufacturers can select an appropriate test setup. Committee(s): JC-70.2 Free download. Registration or login required.
LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES	JEP160A	Aug 2022
This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
RECOMMENDED ESD-CDM TARGET LEVELS	JEP157A	Apr 2022
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices	JEP151A	Jan 2022
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications. Committee(s): JC-14.1 Free download. Registration or login required.

Standards & Documents Search

ECXML Guidelines for Electronic Thermal System Level Models – XML Requirements Schema

Guideline for Evaluating Bipolar Degradation of Silicon Carbide Power Devices

Guideline for Reverse Bias Reliability Evaluation Procedures for Gallium Nitride Power Conversion Devices

JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES

GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTS

Guidelines for Particle Impact Noise Detection (PIND) Testing, Operator Training, and Certification

Guidelines for Supplier Performance Rating

Guidelines for Packing and Labeling of Integrated Circuits in Unit Container Packing (Tubes, Trays, and Tape and Reel)

Guideline for Evaluating Gate Switching Instability of Silicon Carbide Metal-Oxide-Semiconductor Devices for Power Electronic Conversion

Guideline for Gate Oxide Reliability and Robustness Evaluation Procedures for Silicon Carbide Power MOSFETs

Guidelines for Measuring the Threshold Voltage (VT) of SiC MOSFETs

Guidelines for Gate Charge (QG) Test Method for SiC MOSFET

SELECTION OF BURN-IN / LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS

Survey On Latch-Up Testing Practices and Recommendations for Improvements

PROCESS CHARACTERIZATION GUIDELINE

SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED)

Guideline for Evaluating dv/dt Robustness of SiC Power Devices, Version 1.0

LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES

RECOMMENDED ESD-CDM TARGET LEVELS

Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices

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