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Title	Document #	Date
Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs	JEP183A	Jan 2023
This publication describes the guidelines for VT measurement methods and conditioning prior to VT testing in SiC power MOSFETs to reduce or eliminate the effect of the aforementioned hysteresis. Committee(s): JC-70.1 Free download. Registration or login required.
SELECTION OF BURN-IN / LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS	JEP163A	Jan 2023
This publication is a guideline to assist manufacturers of integrated circuits in defining conditions for burn-in and life test of their products to meet quality and reliability performance requirements of MIL-PRF-38535. Committee(s): JC-13, JC-13.2 Free download. Registration or login required.
Guidelines for Gate Charge (QG) Test Method for SiC MOSFET	JEP192	Jan 2023
This publication defines a QGS, TOT, QGD and QGS, TH which can be extracted from a measured QG waveform for SiC MOSFETs. Committee(s): JC-70, JC-70.2 Free download. Registration or login required.
Survey On Latch-Up Testing Practices and Recommendations for Improvements	JEP193	Jan 2023
This is a re-publication of a white paper which reports on a survey that has been conducted to better understand how the latch-up standard JESD78 revision E (JESD78E) is interpreted and has been used in the industry. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
PROCESS CHARACTERIZATION GUIDELINE	JEP132A.01	Dec 2022
This guideline provides a methodology to characterize a new or existing process and is applicable to any manufacturing or service process. It describes when to use specific tools such as failure mode effects analysis (FEMA), design or experiments (DOE), measurement system evaluation (MSE), capability analysis (CpK), statistical process control (SPC), and problem solving tools. It also provides a brief description of each tool. Committee(s): JC-13 Free download. Registration or login required.
STANDARD MANUFACTURERS IDENTIFICATION CODE NOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded.	JEP106BF	Oct 2022
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED)	JEP164	Oct 2022
This white paper presents the recent knowledge of system ESD field events and air discharge testing methods. Testing experience with the IEC 61000-4-2 (2008) and the ISO 10605 ESD standards has shown a range of differing interpretations of the test method and its scope. This often results in misapplication of the test method and a high test result uncertainty. This white paper aims to explain the problems observed and to suggest improvements to the ESD test standard and to enable a correlation with a SEED IC/PCB co-design methodology. Committee(s): JC-14.3 Free download. Registration or login required.
Guideline for Evaluating dv/dt Robustness of SiC Power Devices, Version 1.0	JEP190	Aug 2022
This document provides stress procedures, general failure criteria and documentation guidelines such that the dv/dt robustness can be demonstrated, evaluated and documented. This document gives examples for test setups which can be used and the corresponding test conditions. Additionally, criteria are explained under which device manufacturers can select an appropriate test setup. Committee(s): JC-70.2 Free download. Registration or login required.
LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES	JEP160A	Aug 2022
This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
RECOMMENDED ESD-CDM TARGET LEVELS	JEP157A	Apr 2022
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices	JEP151A	Jan 2022
This test method defines the requirements and procedures for terrestrial destructive* single-event effects (SEE) for example, single-event breakdown (SEB), single-event latch-up (SEL) and single-event gate rupture (SEGR) testing . It is valid when using an accelerator, generating a nucleon beam of either; 1) Mono-energetic protons or mono-energetic neutrons of at least 150 MeV energy, or 2) Neutrons from a spallation spectrum with maximum energy of at least 150 MeV. This test method does not apply to testing that uses beams with particles heavier than protons. *This test method addresses a separate risk than does JESD89 tests for non-destructive SEE due to cosmic radiation effects on terrestrial applications. Committee(s): JC-14.1 Free download. Registration or login required.
Guidelines for Representing Switching Losses of SIC MOSFETs in Datasheets	JEP187	Dec 2021
This document describes the impact of measurement and/or setup parameters on switching losses of power semiconductor switches; focusing primarily on SiC MOSFET turn-on losses. In terms of turn-off losses, the behavior of SiC MOSFETs is similar to that of existing silicon based power MOSFETs, and as such are adequately represented in typical datasheets. Committee(s): JC-70.2 Free download. Registration or login required.
Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0	JEP186	Dec 2021
This guideline describes different techniques for specifying a Transient Off-state Withstand Voltage Robustness Indicator in datasheets for lateral GaN power conversion devices. This guideline does not convey preferences for any of the specification types presented, nor does the guideline address formatting of datasheets. This guideline does not indicate nor require that the datasheet parameters are used in production tests, nor specify how the values were obtained. Committee(s): JC-70.1 Free download. Registration or login required.
COPY-EXACT PROCESS FOR MANUFACTURING	JEP185	Aug 2021
This publication defines the requirements for Copy-Exact Process (CEP) matching, real-time process control, monitoring, and ongoing assessment of the CEP. The critical element requirements for inputs, process controls, procedures, process indicators, human factors, equipment/infrastructure and matching outputs are given. Manufacturers, suppliers and their customers may use these methods to define requirements for process transfer within the constraints of their business agreements. Committee(s): JC-14.3 Free download. Registration or login required.
JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES	JEP166D	Apr 2021
This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories Committee(s): JC-42.6 Free download. Registration or login required.
ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING – REPORTING ESD WITHSTAND LEVELS ON DATASHEETS	JEP178	Apr 2021
This document is intended to guide device manufacturers in developing datasheets and to device customers in understanding datasheet entries. Committee(s): JC-14.3 Free download. Registration or login required.
GUIDELINE FOR EVALUATING BIAS TEMPERATURE INSTABILITY OF SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR DEVICES FOR POWER ELECTRONIC CONVERSION	JEP184	Mar 2021
The scope of this document covers SiC-based PECS devices having a gate dielectric region biased to turn devices on and off. This typically refers to MOS devices such as MOSFETs and IGBTs. In this document, only NMOS devices are discussed as these are dominant for power device applications; however, the procedures apply to PMOS devices as well. Committee(s): JC-70.2 Free download. Registration or login required.
NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION	JEP300-1	Mar 2021
RAM process node transistor scaling for power and DRAM capacity has made DRAM cells more sensitive to disturbances or transient faults. This sensitivity becomes much worse if external stresses are applied in a meticulously manipulated sequence, such as Rowhammer. Rowhammer related papers have been written outside of JEDEC, but some assumptions used in those papers didn’t explain the problem very clearly or correctly, so the perception for this matter is not precisely understood within the industry. This publication defines the problem and recommends following mitigations to address such concerns across the DRAM industry or academia. Item 1866.01. Committee(s): JC-42 Free download. Registration or login required.
SYSTEM LEVEL ROWHAMMER MITIGATION	JEP301-1	Mar 2021
A DRAM rowhammer security exploit is a serious threat to cloud service providers, data centers, laptops, smart phones, self-driving cars and IoT devices. Hardware research and development will take time. DRAM components, DRAM DIMMs, System-on-chip (SoC), chipsets and system products have their own design cycle time and overall life time. This publication recommends best practices to mitigate the security risks from rowhammer attacks. Item 1866.02. Committee(s): JC-42 Free download. Registration or login required.
GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES	JEP180.01	Jan 2021
This document is intended for use by GaN product suppliers and related power electronic industries. It provides guidelines for evaluating the switching reliability of GaN power switches and assuring their reliable use in power conversion applications. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions and cascode GaN power switches. Committee(s): JC-70.1 Free download. Registration or login required.

Standards & Documents Search

Guidelines for measuring the threshold voltage (VT) of SiC MOSFETs

SELECTION OF BURN-IN / LIFE TEST CONDITIONS AND CRITICAL PARAMETERS FOR QML MICROCIRCUITS

Guidelines for Gate Charge (QG) Test Method for SiC MOSFET

Survey On Latch-Up Testing Practices and Recommendations for Improvements

PROCESS CHARACTERIZATION GUIDELINE

STANDARD MANUFACTURERS IDENTIFICATION CODE

SYSTEM LEVEL ESD Part III: Review of ESD Testing and Impact on System-Efficient ESD Design (SEED)

Guideline for Evaluating dv/dt Robustness of SiC Power Devices, Version 1.0

LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES

RECOMMENDED ESD-CDM TARGET LEVELS

Test Procedure for the Measurement of Terrestrial Cosmic Ray Induced Destructive Effects in Power Semiconductor Devices

Guidelines for Representing Switching Losses of SIC MOSFETs in Datasheets

Guideline to Specify a Transient Off-State Withstand Voltage Robustness Indicator in Datasheets for Lateral GaN Power Conversion Devices, Version 1.0

COPY-EXACT PROCESS FOR MANUFACTURING

JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES

ELECTROSTATIC DISCHARGE (ESD) SENSITIVITY TESTING – REPORTING ESD WITHSTAND LEVELS ON DATASHEETS

GUIDELINE FOR EVALUATING BIAS TEMPERATURE INSTABILITY OF SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR DEVICES FOR POWER ELECTRONIC CONVERSION

NEAR-TERM DRAM LEVEL ROWHAMMER MITIGATION

SYSTEM LEVEL ROWHAMMER MITIGATION

GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES

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