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Title	Document #	Date
STANDARD MANUFACTURERS IDENTIFICATION CODE NOTE: JEP106U was in error starting with bank two an additional continuation code was added, JEP106U should be discarded.	JEP106BB	Jun 2020
The manufacturers identification code is defined by one or more 8 bit fields, each consisting of 7 data bits plus 1 odd parity bit. The manufacturers identification code is assigned, maintained and updated by the JEDEC Office. The intent of this identification code is that it may be used whenever a digital field is required, e.g., hardware, software, documentation, etc. To make a request for an ID Code please go to http://www.jedec.org/Home/MIDCODE_request.cfm Committee(s): JC-42, JC-42.3 Free download. Registration or login required.
GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES	JEP180	Feb 2020
This document is intended for use by GaN product suppliers and related power electronic industries. It provides guidelines for evaluating the switching reliability of GaN power switches and assuring their reliable use in power conversion applications. It is applicable to planar enhancement-mode, depletion-mode, GaN integrated power solutions and cascode GaN power switches. Committee(s): JC-70.1 Free download. Registration or login required.
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS	JEP162A	Sep 2019
JEP162A, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
DYNAMIC ON-RESISTANCE TEST METHOD GUIDELINES FOR GaN HEMT BASED POWER CONVERSION DEVICES, VERSION 1.0	JEP173	Jan 2019
This document is intended for use in the GaN power semiconductor and related power electronic industries, and provides guidelines for measuring the dynamic ON-resistance of GaN power devices. Committee(s): JC-70.1 Free download. Registration or login required.
SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES	JEP143D	Jan 2019
The purpose of this publication is to provide an overview of some of the most commonly used systems and test methods historically performed by manufacturers to assess and qualify the reliability of solid state products. The appropriate references to existing and proposed JEDEC (or EIA) standards and publications are cited. This document is also intended to provide an educational background and overview of some of the technical and economic factors associated with assessing and qualifying microcircuit reliability. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
GUIDELINES FOR GaAs MMIC PHEMT/MESFET AND HBT RELIABILITY ACCELERATED LIFE TESTING	JEP118A	Dec 2018
These guidelines apply to GaAs Monolithic Microwave Integrated Circuits (MMICs) and their individual component building blocks, such as GaAs Metal-Semiconductor Field Effect Transistors (MESFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs), Heterojunction Bipolar Transistors (HBTs), resistors, and capacitors. While the procedure described in this document may be applied to other semiconductor technologies, especially those used in RF and microwave frequency analog applications, it is primarily intended for technologies based on GaAs and related III-V material systems (InP, AlGaAs, InGaAs, InGaP, GaN, etc). Committee(s): JC-14.7 Free download. Registration or login required.
FOUNDRY PROCESS QUALIFICATION GUIDELINES – PRODUCT LEVEL (Wafer Fabrication Manufacturing Sites)	JEP001-3A	Sep 2018
This document describes package-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required.
FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites)	JEP001-1A	Sep 2018
This document describes backend-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required.
FOUNDRY PROCESS QUALIFICATION GUIDELINES - FRONT END TRANSISTOR LEVEL (Wafer Fabrication Manufacturing Sites)	JEP001-2A	Sep 2018
This document describes transistor-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required.
POTENTIAL FAILURE MODE AND EFFECTS ANALYSIS (FMEA)	JEP131C	Aug 2018
This publication applies to electronic components and subassemblies product and or process development, manufacturing processes and the associated performance requirements in customer applications. These areas should include, but are not limited to: package design, chip design, process development, assembly, fabrication, manufacturing, materials, quality, service, and suppliers, as well as the process requirements needed for the next assembly. Committee(s): JC-14.4 Free download. Registration or login required.
PROCESS CHARACTERIZATION GUIDELINE	JEP132A	Aug 2018
This guideline provides a methodology to characterize a new or existing process and is applicable to any manufacturing or service process. It describes when to use specific tools such as failure mode effects analysis (FEMA), design or experiments (DOE), measurement system evaluation (MSE), capability analysis (CpK), statistical process control (SPC), and problem solving tools. It also provides a brief description of each tool. Committee(s): JC-13 Free download. Registration or login required.
JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES	JEP166C	Jul 2018
This document defines the JC-42.6 Manufacturer ID. This document covers Manufacturer ID Codes for the following technologies: LPDDR (JESD209), LPDDR2 (JESD209-2), LPDDR3 (JESD209-3), LPDDR4 (JESD209-4), Wide-IO (JESD229), and Wide-IO2 (JESD229-2). The purpose of this document is to define the Manufacturer ID for these devices. Item No. 1725.03C. See Annex for additions/changes. To make a request for an ID code: https://www.jedec.org/id-codes-low-power-memories Committee(s): JC-42.6 Free download. Registration or login required.
RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION	JEP155B	Jul 2018
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD level requirements. It will be shown through this document why realistic modifying of the ESD target levels for component level ESD is not only essential but is also urgent. The document is organized in different sections to give as many technical details as possible to support the purpose given in the abstract. In June 2009 the formulating committee approved the addition of the ESDA logo on the covers of this document. Please see Annex C for revision history. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
PART MODEL PACKAGE GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS	JEP30-P100.01	May 2018
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, thermal, assembly process classification data along with materials and substances that may be present in the supplied product or sub-products. This Guideline specifically focuses on the "Package" subsection of the Part Model. Committee(s): JC-11.2 Free download. Registration or login required.
PART MODEL ELECTRICAL GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS	JEP30-E100	Apr 2018
This standard establishes the requirements for exchanging part data between part manufacturers and their customers for electrical and electronic products. This standard applies to all forms of electronic parts. It forms part of the Part Model XML Schema, which covers the parental structure for the electrical, physical, Electrical, assembly process classification data along with materials and substances that may be present in the supplied product or subproducts. This Guideline specifically focuses on the “Electrical” sub-section of the Part Model. Committee(s): JC-11.2 Free download. Registration or login required.
PART MODEL ELECTRICAL SCHEMA	JEP30-E101X	Apr 2018
In conjunction with JEP30-E100, for user support, this file is the entire “Part Model Electrical Schema” (JEP30-10 Part Model Schema, JEP30-e101 Part Model Thermal Schema, and JEP30-D10 Part Model Schema Types Dictionary). Committee(s): JC-11.2 Free download. Registration or login required.
PART MODEL PACKAGE SCHEMA	JEP30-P101X	Mar 2018
In conjunction with JEP30-P100, for user support thiis file is the entire “Part Model Package Schema” (JEP30-10 Part Model Schema, JEP30-P101 Part Model Package Schema, and JEP30-D10 Part Model Schema Types Dictionary). Committee(s): JC-11 Free download. Registration or login required.
PART MODEL ASSEMBLY PROCESS CLASSIFICATION SCHEMA	JEP30-A101X	Mar 2018
In conjunction with JEP30-A100, for user support this file is the entire “Part Model Assembly Process Classification Schema” (JEP30-10 Part Model Schema, JEP30-A101 Part Model Assembly Process Classification Schema, and JEP30-D10 Part Model Schema Types Dictionary). Committee(s): JC-11 Free download. Registration or login required.
PART MODEL THERMAL SCHEMA	JEP30-T101X	Mar 2018
In conjunction with JEP30-T100, for user support, this file is the entire “Part Model Thermal Schema” (JEP30-10 Part Model Schema, JEP30-T101 Part Model Thermal Schema, and JEP30-D10 Part Model Schema Types Dictionary). Committee(s): JC-11 Free download. Registration or login required.
CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION	JEP156A	Mar 2018
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.

Standards & Documents Search

STANDARD MANUFACTURERS IDENTIFICATION CODE

GUIDELINE FOR SWITCHING RELIABILITY EVALUATION PROCEDURES FOR GALLIUM NITRIDE POWER CONVERSION DEVICES

SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS

DYNAMIC ON-RESISTANCE TEST METHOD GUIDELINES FOR GaN HEMT BASED POWER CONVERSION DEVICES, VERSION 1.0

SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES

GUIDELINES FOR GaAs MMIC PHEMT/MESFET AND HBT RELIABILITY ACCELERATED LIFE TESTING

FOUNDRY PROCESS QUALIFICATION GUIDELINES – PRODUCT LEVEL (Wafer Fabrication Manufacturing Sites)

FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites)

FOUNDRY PROCESS QUALIFICATION GUIDELINES - FRONT END TRANSISTOR LEVEL (Wafer Fabrication Manufacturing Sites)

POTENTIAL FAILURE MODE AND EFFECTS ANALYSIS (FMEA)

PROCESS CHARACTERIZATION GUIDELINE

JC-42.6 MANUFACTURER IDENTIFICATION (ID) CODE FOR LOW POWER MEMORIES

RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION

PART MODEL PACKAGE GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS

PART MODEL ELECTRICAL GUIDELINES FOR ELECTRONIC-DEVICE PACKAGES – XML REQUIREMENTS

PART MODEL ELECTRICAL SCHEMA

PART MODEL PACKAGE SCHEMA

PART MODEL ASSEMBLY PROCESS CLASSIFICATION SCHEMA

PART MODEL THERMAL SCHEMA

CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION

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