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Title	Document #	Date
ANNUAL UPDATING SERVICE:	JEP95 AUS	Jan 2000
Subscription to this updating service is available from the JEDEC Office. New outlines are shipped to subscribers for insertion into the appropriate sections of Publication No. 95. JEP95 and Updating Service can be ordered through JEDEC at (703)907-7540 or ptanner@jedec.org. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-11
ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES	JEP176	Jan 2018
This publication describes guidelines for applying JEDEC reliability tests and recommended testing procedures to integrated circuits that require adapter test boards for electrical and reliability testing. These tests are used frequently in qualifying integrated circuits as a new product, a product family, or as products in a process which is being changed. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.3 Free download. Registration or login required.
A PROCEDURE FOR EXECUTING SWEAT: Status: Reaffirmed October 2012, September 2018, April 2025	JEP119A	Aug 2003
This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some test-structures design features are provided in JESD87 and in ASTM 1259M - 96. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14.2 Free download. Registration or login required.
A Case for Lowering Component-level CDM ESD Specifications and Requirements Part II: Die-to-Die Interfaces	JEP196	Nov 2023
This white paper presents an industry-wide survey on the relevance of industry-aligned D2D CDM targets and the currently used targets for D2D interfaces. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions	JEP158	Nov 2009
To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
GUIDELINE FOR EVALUATING BIAS TEMPERATURE INSTABILITY OF SILICON CARBIDE METAL-OXIDE-SEMICONDUCTOR DEVICES FOR POWER ELECTRONIC CONVERSION	JEP184	Mar 2021
The scope of this document covers SiC-based PECS devices having a gate dielectric region biased to turn devices on and off. This typically refers to MOS devices such as MOSFETs and IGBTs. In this document, only NMOS devices are discussed as these are dominant for power device applications; however, the procedures apply to PMOS devices as well. A list of RAND License Assurance/Disclosure Forms is available to JEDEC members on the restricted Members' website. Non-members may obtain individual Assurance/Disclosure forms by requesting them from the JEDEC office. Committee(s): JC-70.2 Free download. Registration or login required.

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