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Title	Document #	Date
TEST PROCEDURES FOR CUSTOM MONOLITHIC MICROCIRCUITS - SUPERSEDED BY MIL-PRF-38535C. Status: RescindedJun-96	JEP111	Jan 1986
Committee(s): JC-13, JC-13.2
RECOMMENDED PRACTICE FOR DUAL DIMENSIONING Status: Rescinded	JEP86-A	Jan 1976
Committee(s): JC-11
THERMAL RESISTANCE AND THERMAL IMPEDANCE TEST METHODS FOR STUD AND BASE-MOUNTED RECTIFIER DIODES AND THYRISTORS Status: Rescinded	JEP88	Jan 1974
Committee(s): JC-22.1
ANNUAL UPDATING SERVICE:	JEP95 AUS	Jan 2000
Subscription to this updating service is available from the JEDEC Office. New outlines are shipped to subscribers for insertion into the appropriate sections of Publication No. 95. JEP95 and Updating Service can be ordered through JEDEC at (703)907-7540 or ptanner@jedec.org. Committee(s): JC-11
GUIDELINES FOR NONDESTRUCTIVE PULL TESTING OF WIRE BONDS ON HYBRID DEVICES Status: Rescinded	JEP96	Jan 1977
Committee(s): JC-13.5
MICROELECTRONIC DEVICE TYPE ASSIGNMENTS Status: RescindedJun-92	JEP93	Jan 1975
Committee(s): JCJEDC
GUIDELINE FOR MEASUREMENT OF ELECTRONIC PACKAGE INDUCTANCE AND CAPACITANCE MODEL PARAMETERS:	JEP123	Oct 1995
The need for this guideline arose from widespread lack of consistency in characterizing electrical parameters of electronic packages, which existed in the industry until the early 1990s. Then, the JEDEC Committee JC-15 provided the forum where various methods were discussed and commonality in approach emerged. The result is that today we have relatively consistent results in measuring and reporting electrical package parameters, as well as specialized tools (e.g., the IPA-510, the interconnect parameter analyzer) which were developed to support the methodology. Committee(s): JC-15.2, JC-15 Free download. Registration or login required.
GUIDE FOR THE PRODUCTION AND ACQUISITION OF RADIATION-HARDNESS ASSURED MULTICHIP MODULES AND HYBRID MICROCIRCUITS:	JEP133C	Jan 2010
A revised and expanded publication for suppliers and users of radiation hardness assured (RHA) multichip modules (MCMs) and hybrid microcircuits, is now available. The document provides guidance as to how to achieve, maintain and ensure required levels of radiation-hardness given the fact that the constituent dice can have different levels of hardness assurance. It also describes how to deal with the various radiation hardness situations that an MCM/Hybrid developer, procuring activity or user will encounter. The guide is intended to supplement three relevant performance specifications: MIL-PRF-38534, MIL-PRF-38535 and MIL-PRF-19500. Committee(s): JC-13.5, JC-13.4 Free download. Registration or login required.
JEDEC REGISTERED AND STANDARD OUTLINES FOR SOLID STATE AND RELATED PRODUCTS:	JEP95	Jan 2000
This publication is a compilation of some 1800 pages of outline drawings for microelectronic packages including transistors, diodes, DIPS, chip carriers and package interface BGA outlines in both inch and metric versions. Committee(s): JC-11 See JEP95 information
3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions	JEP158	Nov 2009
To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
GUIDELINE FOR INTERNAL GAS ANALYSIS FOR MICROELECTRONIC PACKAGES Status: Reaffirmed November 2020	JEP144A	Nov 2011
This guideline is applicable to hermetically sealed microelectronic components (including discrete semiconductors, monolithic and hybrid microcircuits). Specific cases with unique packaging, materials, or environmental constraints may not find all of the following information and procedures applicable. Committee(s): JC-13 Free download. Registration or login required.
POTENTIAL FAILURE MODE AND EFFECTS ANALYSIS (FMEA)	JEP131C	Aug 2018
This publication applies to electronic components and subassemblies product and or process development, manufacturing processes and the associated performance requirements in customer applications. These areas should include, but are not limited to: package design, chip design, process development, assembly, fabrication, manufacturing, materials, quality, service, and suppliers, as well as the process requirements needed for the next assembly. Committee(s): JC-14.4 Free download. Registration or login required.
SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES	JEP143D	Jan 2019
The purpose of this publication is to provide an overview of some of the most commonly used systems and test methods historically performed by manufacturers to assess and qualify the reliability of solid state products. The appropriate references to existing and proposed JEDEC (or EIA) standards and publications are cited. This document is also intended to provide an educational background and overview of some of the technical and economic factors associated with assessing and qualifying microcircuit reliability. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES	JEP160A	Aug 2022
This publication examines the LTS requirements of wafers, dice, and packaged solid-state devices. The user should evaluate and choose the best practices to ensure their product will maintain as-received device integrity and minimize age- and storage-related degradation effects. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES	JEP167A	Nov 2020
This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle. Committee(s): JC-14.1 Free download. Registration or login required.
RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION Status: Reaffirmed January 2024	JEP155B	Jul 2018
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD level requirements. It will be shown through this document why realistic modifying of the ESD target levels for component level ESD is not only essential but is also urgent. The document is organized in different sections to give as many technical details as possible to support the purpose given in the abstract. In June 2009 the formulating committee approved the addition of the ESDA logo on the covers of this document. Please see Annex C for revision history. Reaffirmed: January 2024 Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
RECOMMENDED ESD-CDM TARGET LEVELS	JEP157A	Apr 2022
This document was written with the intent to provide information for quality organizations in both semiconductor companies and their customers to assess and make decisions on safe ESD CDM level requirements. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS This is an editorial revision, details can be found in Annex F.	JEP162A.01	Jan 2021
This document, while establishing the complex nature of System Level ESD, proposes that an efficient ESD design can only be achieved when the interaction of the various components under ESD conditions are analyzed at the system level. This objective requires an appropriate characterization of the components and a methodology to assess the entire system using simulation data. This is applicable to system failures of different categories (such as hard, soft, and electromagnetic interference (EMI)). This type of systematic approach is long overdue and represents an advanced design approach which replaces the misconception, as discussed in detail in JEP161, that a system will be sufficiently robust if all components exceed a certain ESD level. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
GUIDE TO STANDARDS AND PUBLICATIONS RELATING TO QUALITY AND RELIABILITY OF ELECTRONIC HARDWARE	JEP70C	Oct 2013
This document gathers and organizes common standards and publications relating to quality processes and methods relating to the solid-state, microelectronics, and associated industries. This is intended to facilitate access to the applicable documents when working with electronic hardware. This will have a positive effect on quality and reliability as users gain more access to proper methods in designing, producing, and testing parts. Committee(s): JC-14.4 Free download. Registration or login required.
RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES BASED ON PHYSICS OF FAILURE RISK AND OPPORTUNITY ASSESSMENT Status: Reaffirmed September 2019	JEP148B	Jan 2014
A concept is outlined, which proactively integrates qualification into the development process and provides a systematic procedure as support tool to development and gives early focus on required activities. It converts requirements for a product into measures of development and qualification in combination with a risk and opportunity assessment step and accompanies the development process as guiding and recording tool for advanced quality planning and confirmation. The collected data enlarge the knowledge database for DFR / BIR (design for reliability / building-in reliability) to be used for future projects. The procedure challenges and promotes teamwork of all involved disciplines. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.

Standards & Documents Search

TEST PROCEDURES FOR CUSTOM MONOLITHIC MICROCIRCUITS - SUPERSEDED BY MIL-PRF-38535C.

RECOMMENDED PRACTICE FOR DUAL DIMENSIONING

THERMAL RESISTANCE AND THERMAL IMPEDANCE TEST METHODS FOR STUD AND BASE-MOUNTED RECTIFIER DIODES AND THYRISTORS

ANNUAL UPDATING SERVICE:

GUIDELINES FOR NONDESTRUCTIVE PULL TESTING OF WIRE BONDS ON HYBRID DEVICES

MICROELECTRONIC DEVICE TYPE ASSIGNMENTS

GUIDELINE FOR MEASUREMENT OF ELECTRONIC PACKAGE INDUCTANCE AND CAPACITANCE MODEL PARAMETERS:

GUIDE FOR THE PRODUCTION AND ACQUISITION OF RADIATION-HARDNESS ASSURED MULTICHIP MODULES AND HYBRID MICROCIRCUITS:

JEDEC REGISTERED AND STANDARD OUTLINES FOR SOLID STATE AND RELATED PRODUCTS:

3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions

GUIDELINE FOR INTERNAL GAS ANALYSIS FOR MICROELECTRONIC PACKAGES

POTENTIAL FAILURE MODE AND EFFECTS ANALYSIS (FMEA)

SOLID STATE RELIABILITY ASSESSMENT QUALIFICATION METHODOLOGIES

LONG-TERM STORAGE GUIDELINES FOR ELECTRONIC SOLID-STATE WAFERS, DICE, AND DEVICES

CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES

RECOMMENDED ESD TARGET LEVELS FOR HBM/MM QUALIFICATION

RECOMMENDED ESD-CDM TARGET LEVELS

SYSTEM LEVEL ESD: PART II: IMPLEMENTATION OF EFFECTIVE ESD ROBUST DESIGNS

GUIDE TO STANDARDS AND PUBLICATIONS RELATING TO QUALITY AND RELIABILITY OF ELECTRONIC HARDWARE

RELIABILITY QUALIFICATION OF SEMICONDUCTOR DEVICES BASED ON PHYSICS OF FAILURE RISK AND OPPORTUNITY ASSESSMENT

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