Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions |
JEP158 | Nov 2009 |
To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies. Free download. Registration or login required. |
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A PROCEDURE FOR EXECUTING SWEAT:Status: Reaffirmed October 2012, September 2018 |
JEP119A | Aug 2003 |
This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some test-structures design features are provided in JESD87 and in ASTM 1259M - 96. Committee(s): JC-14.2 Free download. Registration or login required. |
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ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES |
JEP176 | Jan 2018 |
This publication describes guidelines for applying JEDEC reliability tests and recommended testing procedures to integrated circuits that require adapter test boards for electrical andreliability testing. These tests are used frequently in qualifying integrated circuits as a newproduct, a product family, or as products in a process which is being changed. Committee(s): JC-14.3 Free download. Registration or login required. |
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ANNUAL UPDATING SERVICE: |
JEP95 AUS | Jan 2000 |
Subscription to this updating service is available from the JEDEC Office. New outlines are shipped to subscribers for insertion into the appropriate sections of Publication No. 95. JEP95 and Updating Service can be ordered through JEDEC at (703)907-7540 or ptanner@jedec.org. Committee(s): JC-11 |
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APPLICATION THERMAL DERATING METHODOLOGIES:Status: Reaffirmed September 2019 |
JEP149 | Nov 2004 |
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. Free download. Registration or login required. |