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Title	Document #	Date
FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites)	JEP001-1A	Sep 2018
This document describes backend-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required.
GUIDELINE FOR OBTAINING AND ACCEPTING MATERIAL FOR USE IN HYBRID/MCM PRODUCTS Status: Reaffirmed May 2023	JEP142	May 2023
This document provides guidance regarding design considerations, material assessment techniques, and recommendations for material acceptance prior to use in Hybrid/MCM Products. As part of the risk assessment process, both technical requirements and cost should be carefully considered with regard to testing/evaluating the elements of a hybrid microcircuit or Multi-chip Module (MCM) prior to material release for assembly. The intent of this document is to highlight various options that are available to the Hybrid / MCM manufacturer and provide associated guidance, not to impose a specific set of tests. Committee(s): JC-13, JC-13.5 Free download. Registration or login required.
Guideline for Characterizing Solder Bump Electromigration Under Constant Current and Temperature Stress	JEP154A	Mar 2024
This publication describes a method to test the electromigration susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION	JEP156A	Mar 2018
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
Guidelines for Visual Inspection and Control of Flip Chip Type Packages (FCxGA)	JEP170A	Jun 2024
This document provides guidelines for visual inspection and control that ensures quality and reliability of flip chip packaged devices. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
SOLID STATE PRODUCTS REGISTRATION LIST(ORDER FROM TYPE ADMINISTRATION OFFICE) Status: ReaffirmedNovember 2002	JEP64	Jan 1986
This publication includes addenda from 1976 to August 1986. The purpose of this list is to determine release numbers (file numbers) for JEDEC Type Designations. (See page 6 for more information.) Committee(s): JCJEDC
Stress-Test-Driven Qualification of and Failure Mechanisms Associated with Assembled Solid State Surface-Mount Devices	JEP150A	Dec 2023
This publication contains frequently recommended and accepted JEDEC reliability stress tests applied to surface-mount solid state devices. Committee(s): JC-14, JC-14.3 Free download. Registration or login required.
CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPERATURES Status: Reaffirmed September 2019	JEP153A	Mar 2014
This document provides an industry standard method for characterization and monitoring thermal stress test oven temperatures. The procedures described in this document should be used to insure thermal stress test conditions are being achieved and maintained during various test procedures. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
A PROCEDURE FOR EXECUTING SWEAT: Status: Reaffirmed October 2012, September 2018	JEP119A	Aug 2003
This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some test-structures design features are provided in JESD87 and in ASTM 1259M - 96. Committee(s): JC-14.2 Free download. Registration or login required.
GUIDELINE FOR CONSTANT TEMPERATURE AGING TO CHARACTERIZE ALUMINUM INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING: Status: ReaffirmedOctober 2012	JEP139	Dec 2000
This document describes a constant temperature (isothermal) aging method for testing aluminum (Al) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding. This method is valid for metallization/dielectric systems in which the dielectric is deposited onto the metallization at a temperature considerably above the intended use temperature, and above or equal to the deposition temperature of the metal. Although this is a wafer test, it is not a fast (less than 5 minutes per probe) test. It is intended to be used for lifetime prediction and failure analysis, not for production Go-NoGo lot checking. Committee(s): JC-14.2 Free download. Registration or login required.

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JEDEC Education Series: Memory, Mobile & Modules