Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # | Date |
|---|---|---|
TEST PROCEDURES FOR CUSTOM MONOLITHIC MICROCIRCUITS - SUPERSEDED BY MIL-PRF-38535C.Status: RescindedJun-96 |
JEP111 | Jan 1986 |
RECOMMENDED PRACTICE FOR DUAL DIMENSIONINGStatus: Rescinded |
JEP86-A | Jan 1976 |
Committee(s): JC-11 |
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THERMAL RESISTANCE AND THERMAL IMPEDANCE TEST METHODS FOR STUD AND BASE-MOUNTED RECTIFIER DIODES AND THYRISTORSStatus: Rescinded |
JEP88 | Jan 1974 |
Committee(s): JC-22.1 |
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ANNUAL UPDATING SERVICE: |
JEP95 AUS | Jan 2000 |
Subscription to this updating service is available from the JEDEC Office. New outlines are shipped to subscribers for insertion into the appropriate sections of Publication No. 95. JEP95 and Updating Service can be ordered through JEDEC at (703)907-7540 or ptanner@jedec.org. Committee(s): JC-11 |
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GUIDELINES FOR NONDESTRUCTIVE PULL TESTING OF WIRE BONDS ON HYBRID DEVICESStatus: Rescinded |
JEP96 | Jan 1977 |
Committee(s): JC-13.5 |
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MICROELECTRONIC DEVICE TYPE ASSIGNMENTSStatus: RescindedJun-92 |
JEP93 | Jan 1975 |
Committee(s): JCJEDC |
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GUIDELINE FOR MEASUREMENT OF ELECTRONIC PACKAGE INDUCTANCE AND CAPACITANCE MODEL PARAMETERS: |
JEP123 | Oct 1995 |
The need for this guideline arose from widespread lack of consistency in characterizing electrical parameters of electronic packages, which existed in the industry until the early 1990s. Then, the JEDEC Committee JC-15 provided the forum where various methods were discussed and commonality in approach emerged. The result is that today we have relatively consistent results in measuring and reporting electrical package parameters, as well as specialized tools (e.g., the IPA-510, the interconnect parameter analyzer) which were developed to support the methodology. Free download. Registration or login required. |
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GUIDE FOR THE PRODUCTION AND ACQUISITION OF RADIATION-HARDNESS ASSURED MULTICHIP MODULES AND HYBRID MICROCIRCUITS: |
JEP133C | Jan 2010 |
A revised and expanded publication for suppliers and users of radiation hardness assured (RHA) multichip modules (MCMs) and hybrid microcircuits, is now available. The document provides guidance as to how to achieve, maintain and ensure required levels of radiation-hardness given the fact that the constituent dice can have different levels of hardness assurance. It also describes how to deal with the various radiation hardness situations that an MCM/Hybrid developer, procuring activity or user will encounter. The guide is intended to supplement three relevant performance specifications: MIL-PRF-38534, MIL-PRF-38535 and MIL-PRF-19500. Committee(s): JC-13.5, JC-13.4 Free download. Registration or login required. |
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JEDEC REGISTERED AND STANDARD OUTLINES FOR SOLID STATE AND RELATED PRODUCTS: |
JEP95 | Jan 2000 |
This publication is a compilation of some 1800 pages of outline drawings for microelectronic packages including transistors, diodes, DIPS, chip carriers and package interface BGA outlines in both inch and metric versions. Committee(s): JC-11 |
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3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions |
JEP158 | Nov 2009 |
To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies. Free download. Registration or login required. |
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