Global Standards for the Microelectronics Industry
Standards & Documents Search
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Document # | Date |
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3D CHIP STACK WITH THROUGH-SILICON VIAS (TSVS): Identifying, Evaluating and Understanding Reliability Interactions |
JEP158 | Nov 2009 |
To increase device bandwidth, reduce power and shrink form factor, microelectronics manufacturers are implementing three dimensional (3D) chip stacking using through silicon vias (TSVs). Chip stacking with TSVs combines silicon and packaging technologies. As a result, these new structures have unique reliability requirements. This document is a guideline that describes how to evaluate the reliability of 3D TSV silicon assemblies. Free download. Registration or login required. |
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A PROCEDURE FOR EXECUTING SWEAT:Status: Reaffirmed October 2012, September 2018 |
JEP119A | Aug 2003 |
This document describes an algorithm for performing the Standard Wafer Level Electromigration Accelerated Test (SWEAT) method with computer controlled instrumentation. The algorithm requires a separate iterative technique (not provided) to calculate the force current for a given target time to failure. This document does not specify what test structure to use with this procedure. However, users of this algorithm report its effectiveness on both straight-lines and via-terminated test structures. Some test-structures design features are provided in JESD87 and in ASTM 1259M - 96. Committee(s): JC-14.2 Free download. Registration or login required. |
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ADAPTER TEST BOARD RELIABILITY TEST GUIDELINES |
JEP176 | Jan 2018 |
This publication describes guidelines for applying JEDEC reliability tests and recommended testing procedures to integrated circuits that require adapter test boards for electrical andreliability testing. These tests are used frequently in qualifying integrated circuits as a newproduct, a product family, or as products in a process which is being changed. Committee(s): JC-14.3 Free download. Registration or login required. |
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APPLICATION THERMAL DERATING METHODOLOGIES: |
JEP149.01 | Jan 2021 |
This publication applies to the application of integrated circuits and their associated packages in end use designs. It summarizes the methodology of thermal derating and the suitability of such methodologies. Free download. Registration or login required. |
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BEADED THERMOCOUPLE TEMPERATURE MEASUREMENT OF SEMICONDUCTOR PACKAGESStatus: ReaffirmedJune 2006, September 2011, January 2015 |
JEP140 | Jun 2002 |
The beaded thermocouple temperature measurement guideline provides a procedure to accurately and consistently measure the temperature of semiconductor packages during exposure to thermal excursions. The guideline applications can include, but not limited to, temperature profile measurement in reliability test chambers and solder reflow operations that are associated with component assembly to printed wiring boards. Free download. Registration or login required. |
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CHARACTERIZATION AND MONITORING OF THERMAL STRESS TEST OVEN TEMPERATURESStatus: Reaffirmed September 2019 |
JEP153A | Mar 2014 |
This document provides an industry standard method for characterization and monitoring thermal stress test oven temperatures. The procedures described in this document should be used to insure thermal stress test conditions are being achieved and maintained during various test procedures. Free download. Registration or login required. |
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CHARACTERIZATION OF INTERFACIAL ADHESION IN SEMICONDUCTOR PACKAGES |
JEP167A | Nov 2020 |
This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle. Committee(s): JC-14.1 Free download. Registration or login required. |
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CHIP-PACKAGE INTERACTION UNDERSTANDING, IDENTIFICATION AND EVALUATION |
JEP156A | Mar 2018 |
This publication references a set of frequently recommended and accepted JEDEC reliability stress tests. These tests are used for qualifying new and modified technology/ process/ product families, as well as individual solid state surface-mount products. Free download. Registration or login required. |
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DISCONTINUING USE OF THE MACHINE MODEL FOR DEVICE ESD QUALIFICATIONStatus: Reaffirmed September 2020 |
JEP172A | Jul 2015 |
Over the last several decades the so called "machine model" (aka MM) and its application to the required ESD component qualification has been grossly misunderstood. The scope of this JEDEC document is to present evidence to discontinue use of this particular model stress test without incurring any reduction in the IC component's ESD reliability for manufacturing. In this regard, the document's purpose is to provide the necessary technical arguments for strongly recommending no further use of this model for IC qualification. The published document should be used as a reference to propagate this message throughout the industry. Committee(s): JC-14.3 Free download. Registration or login required. |
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DISTRIBUTOR REQUIREMENTS FOR HANDLING ELECTROSTATIC -DISCHARGE SENSITIVE (ESDS) DEVICES: SUPERSEDED BY JESD42, March 1994.Status: Superseded |
JEP108-B | Apr 1991 |
Free download. Registration or login required. |
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FAILURE MECHANISMS AND MODELS FOR SEMICONDUCTOR DEVICES |
JEP122H | Sep 2016 |
This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc. Committee(s): JC-14.2 Available for purchase: $163.00 Add to Cart Paying JEDEC Members may login for free access. |
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FOUNDRY PROCESS QUALIFICATION GUIDELINES - BACKEND OF LIFE (Wafer Fabrication Manufacturing Sites) |
JEP001-1A | Sep 2018 |
This document describes backend-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required. |
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FOUNDRY PROCESS QUALIFICATION GUIDELINES - FRONT END TRANSISTOR LEVEL (Wafer Fabrication Manufacturing Sites) |
JEP001-2A | Sep 2018 |
This document describes transistor-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required. |
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FOUNDRY PROCESS QUALIFICATION GUIDELINES – PRODUCT LEVEL (Wafer Fabrication Manufacturing Sites) |
JEP001-3A | Sep 2018 |
This document describes package-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation. Committee(s): JC-14.2 Free download. Registration or login required. |
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GUIDE FOR STANDARD PROBE PAD SIZES AND LAYOUTS FOR WAFER LEVEL ELECTRICAL TESTING: |
JEP128 | Nov 1996 |
This guide was developed to expedite inter-laboratory experiments used to evaluate or develop standard test methods that involve test-structure measurements or tests. It also facilitates, generally, any electrical tests that require wafer-probe card to make electrical contact to test structures. Widespread use of this guide will afford the efficient and cost-effective use of water-probe test stations because of the need for fewer probe cards and probe-card changes to accommodate the various test structures that may need to be tested. Committee(s): JC-14.2 Free download. Registration or login required. |
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GUIDE TO STANDARDS AND PUBLICATIONS RELATING TO QUALITY AND RELIABILITY OF ELECTRONIC HARDWARE |
JEP70C | Oct 2013 |
This document gathers and organizes common standards and publications relating to quality processes and methods relating to the solid-state, microelectronics, and associated industries. This is intended to facilitate access to the applicable documents when working with electronic hardware. This will have a positive effect on quality and reliability as users gain more access to proper methods in designing, producing, and testing parts. Committee(s): JC-14.4 Free download. Registration or login required. |
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GUIDELINE FOR CHARACTERIZING SOLDER BUMP ELECTROMIGRATION UNDER CONSTANT CURRENT AND TEMPERATURE STRESSStatus: ReaffirmedJune 2011 |
JEP154 | Jan 2008 |
This document describes a method to test the electromigration (EM) susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. The method is valid for Sn/Pb eutectic, high Pb, and Pb-free solder bumps. The document discusses the advantages and concerns associated with EM testing, as well as options for data analysis. Free download. Registration or login required. |
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GUIDELINE FOR CONSTANT TEMPERATURE AGING TO CHARACTERIZE ALUMINUM INTERCONNECT METALLIZATIONS FOR STRESS-INDUCED VOIDING:Status: ReaffirmedOctober 2012 |
JEP139 | Dec 2000 |
This document describes a constant temperature (isothermal) aging method for testing aluminum (Al) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding. This method is valid for metallization/dielectric systems in which the dielectric is deposited onto the metallization at a temperature considerably above the intended use temperature, and above or equal to the deposition temperature of the metal. Although this is a wafer test, it is not a fast (less than 5 minutes per probe) test. It is intended to be used for lifetime prediction and failure analysis, not for production Go-NoGo lot checking. Committee(s): JC-14.2 Free download. Registration or login required. |
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GUIDELINES FOR GaAs MMIC PHEMT/MESFET AND HBT RELIABILITY ACCELERATED LIFE TESTING |
JEP118A | Dec 2018 |
These guidelines apply to GaAs Monolithic Microwave Integrated Circuits (MMICs) and their individual component building blocks, such as GaAs Metal-Semiconductor Field Effect Transistors (MESFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs), Heterojunction Bipolar Transistors (HBTs), resistors, and capacitors. While the procedure described in this document may be applied to other semiconductor technologies, especially those used in RF and microwave frequency analog applications, it is primarily intended for technologies based on GaAs and related III-V material systems (InP, AlGaAs, InGaAs, InGaP, GaN, etc). Committee(s): JC-14.7 Free download. Registration or login required. |
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GUIDELINES FOR PACKING AND LABELING OF INTEGRATED CIRCUITS IN UNIT CONTAINER PACKING (Tubes, Trays, and Tape and Reel) |
JEP130B | Nov 2016 |
This document establishes guidelines for integrated circuit unit container and the next level (intermediate) container packing and labeling. The guidelines include tube/rail standardization, intermediate packing, date codes, tube labeling, intermediate container and shipping labels, and standardize tube quantities. Future revisions of this document will also include tray and reel guidelines. The objective of this publication is to promote the standardization of practices between manufacturers and distributors resulting in improved efficiency, profitability, and product quality. Committee(s): JC-14.4 Free download. Registration or login required. |