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This publication describes guidelines for applying JEDEC reliability tests and recommended testing procedures to integrated circuits that require adapter test boards for electrical andreliability testing. These tests are used frequently in qualifying integrated circuits as a newproduct, a product family, or as products in a process which is being changed.

Committee(s): JC-14.3

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The beaded thermocouple temperature measurement guideline provides a procedure to accurately and consistently measure the temperature of semiconductor packages during exposure to thermal excursions. The guideline applications can include, but not limited to, temperature profile measurement in reliability test chambers and solder reflow operations that are associated with component assembly to printed wiring boards.

Committee(s): JC-14, JC-14.1

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This document identifies methods used for the characterization of die adhesion. It gives guidance which method to apply in which phase of the product or technology life cycle.

Committee(s): JC-14.1

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Over the last several decades the so called "machine model" (aka MM) and its application to the required ESD component qualification has been grossly misunderstood. The scope of this JEDEC document is to present evidence to discontinue use of this particular model stress test without incurring any reduction in the IC component's ESD reliability for manufacturing. In this regard, the document's purpose is to provide the necessary technical arguments for strongly recommending no further use of this model for IC qualification. The published document should be used as a reference to propagate this message throughout the industry.

Committee(s): JC-14.3

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This publication provides a list of failure mechanisms and their associated activation energies or acceleration factors that may be used in making system failure rate estimations when the only available data is based on tests performed at accelerated stress test conditions. The method to be used is the Sum-of-the-Failure-Rates method. This publication also provides guidance in the selection of reliability modeling parameters, namely functional form, apparent thermal activation energy values and sensitivity to stresses such as power supply voltage, substrate current, current density, gate voltage, relative humidity, temperature cycling range, mobile ion concentration, etc.

Committee(s): JC-14.2

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This document describes transistor-level test and data methods for the qualification of semiconductor technologies. It does not give pass or fail values or recommend specific test equipment, test structures or test algorithms. Wherever possible, it references applicable JEDEC such as JESD47 or other widely accepted standards for requirements documentation.

Committee(s): JC-14.2

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This guide was developed to expedite inter-laboratory experiments used to evaluate or develop standard test methods that involve test-structure measurements or tests. It also facilitates, generally, any electrical tests that require wafer-probe card to make electrical contact to test structures. Widespread use of this guide will afford the efficient and cost-effective use of water-probe test stations because of the need for fewer probe cards and probe-card changes to accommodate the various test structures that may need to be tested.

Committee(s): JC-14.2

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This document describes a method to test the electromigration (EM) susceptibility of solder bumps, including other types of bumps, such as solder capped copper pillars, used in flip-chip packages. The method is valid for Sn/Pb eutectic, high Pb, and Pb-free solder bumps. The document discusses the advantages and concerns associated with EM testing, as well as options for data analysis.

Committee(s): JC-14, JC-14.1

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These guidelines apply to GaAs Monolithic Microwave Integrated Circuits (MMICs) and their individual component building blocks, such as GaAs Metal-Semiconductor Field Effect Transistors (MESFETs), Pseudomorphic High Electron Mobility Transistors (PHEMTs), Heterojunction Bipolar Transistors (HBTs), resistors, and capacitors.  While the procedure described in this document may be applied to other semiconductor technologies, especially those used in RF and microwave frequency analog applications, it is primarily intended for technologies based on GaAs and related III-V material systems (InP, AlGaAs, InGaAs, InGaP, GaN, etc). 

Committee(s): JC-14.7

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