Global Standards for the Microelectronics Industry
Standards & Documents Search
| Title | Document # |
Date |
|---|---|---|
STEADY-STATE TEMPERATURE-HUMIDITY BIAS LIFE TEST |
JESD22-A101D.01 | Jan 2021 |
This standard establishes a defined method and conditions for performing a temperature-humidity life test with bias applied. The test is used to evaluate the reliability of nonhermetic packaged solid state devices in humid environments. It employs high temperature and humidity conditions to accelerate the penetration of moisture through external protective material or along interfaces between the external protective coating and conductors or other features that pass through it. This revision enhances the ability to perform this test on a device which cannot be biased to achieve very low power dissipation. Free download. Registration or login required. |
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DDR4 NVDIMM-P BUSS PROTOCOL |
JESD304-4 | Nov 2020 |
TEMPORARILY REMOVED 12/8/20. If your downloaded proir to this date please discard this iwill be republished shortly as JESD304-4.01An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory. A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K. Committee(s): JC-45.6 |
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UNIVERSAL FLASH STORAGE (UFS) CARD EXTENSION, Version 3.0 |
JESD220-2B | Nov 2020 |
This standard specifies the characteristics of the UFS card electrical interface and the memory device. This document defines the added/modified features in UFS card compared to embedded UFS device. For other common features JESD220, UFS, will be referenced. Patents(): Samsung: US D727910, US D736212, US D736215, US D736214, US D736213, US 29/546125, US 29/546150 Committee(s): JC-64.1 Available for purchase: $76.00 Add to Cart Paying JEDEC Members may login for free access. |
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CYCLED TEMPERATURE HUMIDITY-BIAS WITH SURFACE CONDENSATION LIFE TEST |
JESD22-A100E | Nov 2020 |
The Cycled Temperature-humidity-bias Life Test is performed for the purpose of evaluating the reliability of nonhermetic packaged solid state devices in humid environments. It employs conditions of temperature cycling, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. The Cycled Temperature-Humidity-Bias Life Test is typically performed on cavity packages (e.g., MQUADs, lidded ceramic pin grid arrays, etc.) as an alternative to JESD22-A101 or JESD22-A110. Free download. Registration or login required. |
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TEMPERATURE CYCLING |
JESD22-A104F | Nov 2020 |
This standard provides a method for determining solid state devices capability to withstand extreme temperature cycling. This standard applies to single-, dual- and triple-chamber temperature cycling and covers component and solder interconnection testing. It should be noted that this standard does not cover or apply to thermal shock chambers. This test is conducted to determine the ability of components and solder interconnects to withstand mechanical stresses induced by alternating high- and low-temperature extremes. Permanent changes in electrical and/or physical characteristics can result from these mechanical stresses. Committee(s): JC-14.1 Free download. Registration or login required. |
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DDRx SPREAD SPECTRUM CLOCKING (SSC) STANDARD |
JESD404-1 | Nov 2020 |
Definition for all DDRx component documents to reference. This is generic to any DDRxtechnology. Item 1842.34 Committee(s): JC-42.3C Free download. Registration or login required. |
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JEDEC MODULE SIDEBAND BUS (SidebandBus) |
JESD403-1 | Oct 2020 |
This standard defines the assumptions for the system management bus for next generation memory solutions; covering the interface protocol, use of hub devices, and voltages appropriate to these usages. Item 2260.37C. Committee(s): JC-45 Free download. Registration or login required. |
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UNIVERSAL FLASH STORAGE, UFS 2.2 |
JESD220C-2.2 | Aug 2020 |
The purpose of this standard is definition of a UFS Universal Flash Storage electrical interface and a UFS memory device. This standard defines a unique UFS feature set and includes the feature set of eMMC standard as a subset. This standard replaces JESD220C, UFS 2.1, and introduces a feature called WriteBooster. Item 138.88. Committee(s): JC-64.1 Free download. Registration or login required. |
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BYTE ADDRESSABLE ENERGY BACKED INTERFACE |
JESD245D | Jul 2020 |
The purpose of this standard is definition of an energy backed byte addressable function on a nonvolatile dual in-line memory module (NVDIMM). This standard defines the feature set and commands implemented by the energy backed byte addressable function on the NVDIMM. This standard is used in conjunction with JESD248. Item 2233.54F * A minor editorial change has been made to the table under 8.1.3.2, on page 47 on 9/1/2020, from the original posted version 8/18/2020. If you downloaded prior to 9/1/2020, please discard and use the current version. Committee(s): JC-45.6 Free download. Registration or login required. |
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DDR5 SDRAM |
JESD79-5 | Jul 2020 |
This document defines the DDR5 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 8Gb through 32Gb for x4, x8, and x16 DDR5 SDRAM devices. This standard was created based on the DDR4 standards (JESD79-4) and some aspects of the DDR, DDR2, DDR3 & LPDDR4 standards (JESD79, JESD79-2, JESD79-3 & JESD209-4). Item 1848.99G. Committee(s): JC-42.3B Available for purchase: $369.00 Add to Cart Paying JEDEC Members may login for free access. |
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TEMPERATURE GRADE AND MEASUREMENT SPECIFICATIONS FOR COMPONENTS AND MODULES |
JESD402-1 | Jul 2020 |
This document specifies standard temperature ranges that may be used, by way of referencing JESD402-1, in other standards, specifications, and datasheets when defining temperature related specifications. Item 1855.01A Committee(s): JC-42 Free download. Registration or login required. |
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PMIC50x0 POWER MANAGEMENT IC SPECIFICATION, Rev. 1 |
JESD301-1 | Jun 2020 |
Definition of PMIC5000, PMIC5010 Voltage Regulator Device for Memory Module Applications Committee(s): JC-40.1 Free download. Registration or login required. |
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PRECONDITIONING OF NONHERMETIC SURFACE MOUNT DEVICES PRIOR TO RELIABILITY TESTING |
JESD22-A113I | Apr 2020 |
This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation. These SMDs should be subjected to the appropriate preconditioning sequence of this document by the semiconductor manufacturer prior to being submitted to specific in-house reliability testing (qualification and reliability monitoring) to evaluate long term reliability (which might be impacted by solder reflow). Committee(s): JC-14.1 Free download. Registration or login required. |
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1.05 V CMOS |
JESD8-34 | Apr 2020 |
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate narrow range 1.05 V CMOS level. Item 159.01 Committee(s): JC-16 Free download. Registration or login required. |
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Addendum No. 1 to JESD79-4, 3D STACKED DRAM |
JESD79-4-1A | Mar 2020 |
This document defines the 3DS DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for a compliant 8 Gbit through 128 Gbit for x4, x8 3DS DDR4 SDRAM devices. This addendum was created based on the JESD79-4 DDR4 SDRAM specification. Each aspect of the changes for 3DS DDR4 SDRAM operation was considered. Item 1727.58F Committee(s): JC-42.3C Free download. Registration or login required. |
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EXPANDED SERIAL PERIPHERAL INTERFACE (xSPI) FOR NON VOLATILE MEMORY DEVICES |
JESD251A | Feb 2020 |
This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a master interface having a low signal count and high data transfer bandwidth with access to multiple sources of slave devices compliant with the interface. It is also, intended for use by peripheral developers or vendors interested in providing slave devices compliant with the standard, including non-volatile memories, volatile memories, graphics peripherals, networking peripherals, FPGAs, sensors, etc. Item 1775.59 and 19-395. Committee(s): JC-42.4 Free download. Registration or login required. |
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SPD5118, SPD5108 HUB AND SERIAL PRESENCE DETECT DEVICE STANDARD |
JESD300-5 | Feb 2020 |
This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a master host bus. The designations SPD5118 and SPD5108 refer to the families of devices specified by this document. The term SPD5 Hub refers generically to both devices in the family. Committee Item 1852.07F. Committee(s): JC-42.4 Free download. Registration or login required. |
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CUSTOMER NOTIFICATION PROCESS FOR DISASTERS |
JESD246A | Jan 2020 |
This standard establishes the requirements for timely notification to affected customers after a disaster has occurred at a supplier’s facility that will affect the committed delivery of product. This standard puts specific emphasis on notification, timing, and notification content which includes risk exposure, impact analysis, and recovery plans. This standard is applicable to suppliers of, and affected customers for, solid-state products and the constituent components used within. Committee(s): JC-14.4 Free download. Registration or login required. |
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LOW POWER DOUBLE DATA RATE 4 (LPDDR4) |
JESD209-4C | Jan 2020 |
This document defines the LPDDR4 standard, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this standard is to define the minimum set of requirements for a JEDEC compliant 16 bit per channel SDRAM device with either one or two channels. LPDDR4 dual channel device density ranges from 4 Gb through 32 Gb and single channel density ranges from 2 Gb through 16 Gb. This document was created using aspects of the following standards: DDR2 (JESD79-2), DDR3 (JESD79-3), DDR4 (JESD79-4), LPDDR (JESD209), LPDDR2 (JESD209-2) and LPDDR3 (JESD209-3). Committee Item: 1847.22 Committee(s): JC-42.6 Available for purchase: $327.00 Add to Cart Paying JEDEC Members may login for free access. |
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UNIVERSAL FLASH STORAGE (UFS) HOST PERFORMANCE BOOSTER (HPB) EXTENSION, VERSION 2.0 |
JESD220-3A | Sep 2020 |
This standard specifies the extension specification of the UFS electrical interface and the memory device. This document describes the extended feature, called Host Performance Booster (HPB), in UFS specification. It also provides some details in how to utilize the HPB for realizing high performance in UFS devices. Committee item 138.34 Patents(): WD: 9,323,657 Committee(s): JC-64.1 Available for purchase: $80.00 Add to Cart Paying JEDEC Members may login for free access. |
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