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Title	Document #	Date
GENERAL STANDARD FOR STATISTICAL PROCESS CONTROL (SPC) - SUPERSEDED by EIA-557-A Status: Rescinded	JESD19	Jul 1988
Committee(s): JC-13 Free download. Registration or login required.
LATCH-UP IN CMOS INTEGRATED CIRCUITS - SUPERSEDED BY JESD78, February 1999 Status: RescindedFebruary 1999	JESD17	Aug 1988
This document is no longer available via the JEDEC website to obtain a copy please contact JEDEC. Committee(s): JC-40.2 Free download. Registration or login required.
ADDENDUM No. 5 to JESD12 - DESIGN FOR TESTABILITY GUIDELINES:	JESD12-5	Aug 1988
This standard is intended to provide circuit designers with the information needed to develop complex integrated circuits that can be reliably and economically tested without compromising flexibility. Committee(s): JC-44 Free download. Registration or login required.
ADDENDUM No. 1 to JESD99, TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR ANALOG-TO-DIGITAL AND DIGITAL-TO-ANALOG CONVERTERS Status: Incorporatedinto JESD99-A, May 2000	JESD99-1	Jul 1989
This addendum has now been incorporated into JESD99. Committee(s): JC-10 Free download. Registration or login required.
ADDENDUM No. 1 to JESD24 - METHOD FOR MEASUREMENT OF POWER DEVICE TURN-OFF SWITCHING LOSS: Status: ReaffirmedApril 1999, October 2002	JESD24- 1	Oct 1989
Describes the method of a typical oscilloscope waveform and the basic test circuit employed in the measurement of turn off loss for bipolar, IGBT and MOSFET power semiconductors. This method can be used as a standard for evaluating power semiconductor turn-off switching loss capability and defines standard terminology that should be referenced within the electronic industry. Committee(s): JC-25 Free download. Registration or login required.
HIGH TEMPERATURE CONTINUITY Status: Rescinded November 1999	JESD22-C100-A	Jan 1990
Committee(s): JC-14.1
STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES: Release Number: Pt 1	JESD20	Jan 1990
This standard describes electrical parameters for this class of CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES: Release Number: Pt 2	JESD20	Jan 1990
This standard describes electrical parameters for this class of CMOS devices. Committee(s): JC-40.2 Free download. Registration or login required.
GENERAL SPECIFICATION FOR PLASTIC ENCAPSULATED MICROCIRCUITS FOR USE IN RUGGED APPLICATIONS - RESCINDED, July 2001 Status: Rescinded	JESD26-A	Apr 1990
Committee(s): JC-13.2 Free download. Registration or login required.
ADDENDUM No. 5 to JESD24 - SINGLE PULSE UNCLAMPED INDUCTIVE SWITCHING (UIS) AVALANCHE TEST METHOD: Status: Reaffirmedoctober 2002	JESD24- 5	Aug 1990
This method describes a means for testing the ability of a power switching device to withstand avalanche breakdown. Committee(s): JC-25 Free download. Registration or login required.
ADDENDUM No. 4 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR BIPOLAR TRANSISTORS (DELTA BASE-EMITTER VOLTAGE METHOD): Status: ReaffirmedOctober 2002	JESD24- 4	Nov 1990
The purpose of this test method is to measure the thermal impedance of the Bipolar Transistor under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity of the base-emitter voltage is used as the junction temperature indicator. This test method is used to measure the thermal response of the junction to a heating pulse. Specifically, the test may be used to measure dc thermal resistance, and to ensure proper die mountdown to its case. This is accomplished through the appropriate choice of pulse duration and heating power magnitude. Committee(s): JC-25 Free download. Registration or login required.
ADDENDUM No. 3 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR VERTICAL POWER MOSFETS (DELTA SOURCE-DRAIN VOLTAGE METHOD): Status: Reaffirmed	JESD24- 3	Nov 1990
The purpose of this test method is to measure the thermal impedance of the MOSFET under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity if the forward voltage drop of the source-drain is used as the junction temperature indicator. This method is particularly suitable to enhancement mode, power MOSFETs having relatively long thermal response times. This test method may be used to measure the thermal response of junction to a heating pulse, to ensure proper die mountdown to its case, or the dc thermal resistance, by the proper choice of the pulse duration and magnitude if the heating pulse. Committee(s): JC-25 Free download. Registration or login required.
ADDENDUM No. 2 to JESD24 - GATE CHARGE TEST METHOD Status: ReaffirmedOctober 2002	JESD24- 2	Jan 1991
This addendum establishes a method for measuring power device gate charge. A gate charge test is performed by driving the device gate with a constant current and measuring the resulting gate voltage response. Constant gate current scales the gate voltage, a function of time, to a function of coulombs. The slope of the generated response reflects the active device capacitance as it varies during the switching transition . Gate charge measurements are useful for characterizing the large signal switching performance of power MOS and IGBT devices. Developed over a four year span by the JEDEC JC-25 Committee, the method defines a repeatable means of measuring the widely published Qgd charge values. Committee(s): JC-25 Free download. Registration or login required.
ADDENDUM No. 6 to JESD12 - INTERFACE STANDARD FOR SEMICUSTOM INTEGRATED CIRCUITS:	JESD12-6	Mar 1991
This standard defines logic interface levels for CMOS, TTL, ECL, and BiCC inputs and outputs. This standard is intended to provide an industry-wide set of specifications, for Application Specific Integrated Circuit (ASIC) signal inputs and outputs, both necessary and sufficient to define a circuits electrical interfacing with the external environment. JESD12-6 is intended to provide the ASIC manufacturer and user with a common set of signal interface levels. The standard defines interface levels for 5 volt operation. Committee(s): JC-44 Free download. Registration or login required.
ADDENDUM No. 6 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR INSULATED GATE BIPOLAR TRANSISTORS: Status: ReaffirmedOctober 2002	JESD24- 6	Oct 1991
This standard describes in detail the method for thermal measurements of Insulated Gate Bipolar Transistors (IGBTs) and is suitable for use both in manufacturing and application of the devices. The method covers both thermal transient and thermal equilibrium measurements for manufacturing process control and device characterization purposes. Properly implemented, JESD24-6 provides a basis for obtaining realistic thermal parametric values that will benefit supplier's internal effectiveness and will be useful to the design and manufacturer of reliable IGBT circuits. Committee(s): JC-25 Free download. Registration or login required.
ADDENDUM No. 9 to JESD24 - SHORT CIRCUIT WITHSTAND TIME TEST METHOD: Status: ReaffirmedOctober 2002	JESD24- 9	Aug 1992
Test method to determine how long a device can survive a short circuit condition with a given drive level. Committee(s): JC-25 Free download. Registration or login required.
ADDENDUM No. 8 to JESD24 - METHOD FOR REPETITIVE INDUCTIVE LOAD AVALANCHE SWITCHING: Status: ReaffirmedOctober 2002	JESD24- 8	Aug 1992
Determines the repetitive inductive avalanche switching capability of power switching transistors. Committee(s): JC-25 Free download. Registration or login required.
CONDITIONS FOR MEASUREMENT OF DIODE STATIC PARAMETERS: Status: ReaffirmedApril 1999, April 2002 (Original publication July 1965)	JESD320-A	Dec 1992
This standard provides guidance for achieving equilibrium when measuring temperature sensitive static parameters of signal diodes. Formerly known as EIA-320-A. Committee(s): JC-22.4 Free download. Registration or login required.
STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC:	JESD18-A	Jan 1993
The purpose of this standard is to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. The standard covers specifications for description of '54/74FCTXXXX' series fast CMOS TTL compatible devices. Committee(s): JC-40.2 Free download. Registration or login required.
FAILURE-MECHANISM-DRIVEN RELIABILITY QUALIFICATION OF SILICON DEVICES Status: Rescinded, November 2004	JESD34	Mar 1993
This document applies to the reliability qualification of new or changed silicon devices, and their materials or manufacturing processes. Does not address qualification of product quality or functionality. Provides an alternative to traditional stress-driven qualification. Committee(s): JC-14.2 Free download. Registration or login required.

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