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This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applications. Any TBDs as of this document, are under discussion by formulating committee. Item 314.11D

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Committee(s): JC-40.4

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Device and Subassembly Mechanical Shock Test Method is intended to evaluate devices in the free state and assembled to printed wiring boards for use in electrical equipment. The method is intended to determine the compatibility of devices and subassemblies to withstand moderately severe shocks. The use of subassemblies is a means to test devices in usage conditions as assembled to printed wiring boards. Mechanical Shock due to suddenly applied forces, or abrupt change in motion produced by handling, transportation or field operation may disturb operating characteristics, particularly if the shock pulses are repetitive. This is a destructive test intended for device qualification.This document also replaces JESD22-B104.

Committee(s): JC-14, JC-14.1

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This document has been replaced by JESD209-5A.  Members of JC-42.6 may access a reference copy on the restricted members' website.

Committee(s): JC-42.6

This stress test is intended to determine the ability of an EEPROM integrated circuit or an integrated circuit with an EEPROM module (such as a microprocessor) to sustain repeated data changes without failure (program/erase endurance) and to retain data for the expected life of the EEPROM (data retention). This Standard specifies the procedural requirements for performing valid endurance and retention tests based on a qualification specification. Endurance and retention qualification specifications (for cycle counts, durations, temperatures, and sample sizes) are specified in JESD47 or may be developed using knowledge-based methods as in JESD94.

Committee(s): JC-14, JC-14.1

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This test method is intended for customers to determine the ability of a device to withstand the mechanical compressive static stress generated when a heat sink is being initially attached to the device, and to help the customer generate design rules for their heat sink design and validate their thermal solution. This test method does not assess the long-term effects of static stress.

Committee(s): JC-14.1

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The purpose of this test method is to identify the potential wave solder classification level of small plastic Surface Mount Devices (SMDs) that are sensitive to moisture-induced stress so that they can be properly packaged, stored, and handled to avoid subsequent mechanical damage during the assembly wave solder attachment and/or repair operations. This test method also provides a reliability preconditioning sequence for small SMDs that are wave soldered using full body immersion. This test method, may be used by users to determine what classification level should be used for initial board level reliability qualification.

Committee(s): JC-14, JC-14.1

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This Test Method covers the minimum requirements that should be in effect for the evaluation and acceptance of polymeric materials for use in industrial, military, space, and other special-condition products which may require capabilities beyond standard commercial microelectronics applications. It is not the intent of this Publication to specify a material, but to evaluate the material to assure that the quality and reliability of the microelectronic devices are not compromised. This document replaces JEP105, JEP107 and JEP112.

Committee(s): JC-13.5

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This document has been superseded by JESD223E, however it is available for reference only.

Committee(s): JC-64.1

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This standard was revised to clarify assumptions necessary to estimate AOQ, revise the minimum sample size algorithm, address small sample size concerns, and provide methods for combining groups for AOQ estimation. Derivation of any new methods for combing groups for AOQ estimation. Derivation of any new methods introduced into this document have been provided in annexes. A statistical method is based on confidence interval statistics. A procedure was established for reporting AOQ when the minimum sample size criterion is not met. Not all sections of EIA-554 are appropriate for use by device manufacturers therefore JEDEC wishes to continue using JESD16. In December 2008 the formulating committee approved to remove EIA-554 (July 1996, Reaffirmed September 2002) from the JEDEC website. To obtain a copy of EIA-554 please contact GEIA at http://www.geia.org/

Committee(s): JC-13

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This document describes a constant temperature (isothermal) aging method for testing copper (Cu) metallization test structures on microelectronics wafers for susceptibility to stress-induced voiding (SIV). This method is to be conducted primarily at the wafer level of production during technology development, and the results are to be used for lifetime prediction and failure analysis. Under some conditions, the method may be applied to package-level testing. This method is not intended to check production lots for shipment, because of the long test time.

Committee(s): JC-14.2

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JESD224A is valid only for UFS 2.1 and should not be referenced for other versions of the UFS standard.

The primary objective of this test standard is to specify the test cases for UFS device protocol conformance testing. This test standard provides test cases for checking the functions defined in the following target standard: JESD220. Universal Flash Storage (UFS) Standard version 1.1A. MIPI M-PHY and MIPI UniPro test cases are not in the scope of this document. Item 400.36

Committee(s): JC-64.5

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The purpose of this JEDEC standard is to verify the workmanship and requirements of microelectronic packages and covers (lids) intended for use in fabricating hybrid microelectronic circuits/microcircuits (hereafter referred to as “microcircuits”). It is applicable for use by the package manufacturer (i.e., package components), and the microcircuit manufacturer (i.e., from incoming inspection of package components through final inspection of the completed microcircuit). This standard also encompasses and replaces JESD27, Ceramic Package Specification for Microelectronic Packages. It is meant to be used in conjunction, and to not contradict, with MIL-STD-883, Test Method 2009: External Visual.

Committee(s): JC-13, JC-13.5

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This method establishes requirements for application of Statistical Reliability Monitoring 'SRM' technology to monitor and improve the reliability of electronic components and subassemblies. The standard also describes the condition under with a monitor may be replaced or eliminated. Formerly known as EIA-659, that superseded JESD29-A (July 1996). Became JESD659 after revision, September 1999.

Committee(s): JC-14, JC-14.3

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This test method provides various tests for determining the integrity lead/package interface and the lead itself when the lead(s) are bent due to faulty board assembly followed by rework of the part for reassembly. For hermetic packages it is recommend that this test be followed by hermeticity tests in accordance with Test Method A109 to determine if there are any adverse effects from the stresses applied to the seals as well as to the leads. These tests, including each of its test conditions, is considered destructive and is only recommended for qualification testing. This test is applicable to all through-hole devices and surface-mount devices requiring lead forming by the user.

Committee(s): JC-14, JC-14.1

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This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board.

Committee(s): JC-14.1

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This document provides a comprehensive definition of the e•MMC Security requirements for implementation of IEEE 1667 and TCG Opal security functionality. It also provides design guidelines and defines a tool box of macro functions and algorithms intended to reduce design-in overhead.

Committee(s): JC-64.1

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This document describes a test method only; acceptance criteria and qualification requirements are not defined. This test method applies to solder ball pull force/energy testing prior to end-use attachment. Solder balls are pulled individually using mechanical jaws; force, fracture energy and failure mode data are collected and analyzed. Other specialized solder ball pull methods using a heated thermode, gang pulling of multiple solder joints, etc., are outside the scope of this document. Both low and high speed testing are covered by this document. This is a minor editorial revision to JESD22-A115A.

Committee(s): JC-14, JC-14.1

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This Unified Memory Extension standard is an extension to the UFSHCI standard, JESD223. The UFSHCI standard defines the interface between the UFS driver and the UFS host controller. In addition to the register interface, it defines data structures inside the system memory, which are used to exchange data, control and status information. Furthermore the UFSHCI standard defines the protocol layer structure and abstract entities within these layers. Unified Memory offers the possibility to move Device internal working memory into the system memory to reduce overall system cost and to improve Device performance. Item 203.25

Patents(): Apple: 2010/0250836; Toshiba: P2011-252001, 13/561392, 101126675, 201210272624.X, 13/758090, 101132071, 201210332970.2, P2012-194380, P2012-194380, P2012-194380; Memory Technology: 2013/0198434, 2010/0312947

Committee(s): JC-64.1

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This document has been superseded by JESD223D, January 2018, however is available for reference only.

Committee(s): JC-64.1

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This Bias Temperature Instability (BTI) stress/test procedure is proposed to provide a minimum recommendation for a simple and consistent comparison of the mean threshold voltage (Vth) BTI induced shift. The procedure enables comparison of stable and manufacturable CMOS processes and technologies in which the process variation is low and the yield is mature. Qualification and accept-reject criteria are not given in this document.

Committee(s): JC-14.2

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The test is applicable for evaluation, screening, monitoring, and/or qualification of all solid state devices Low Temperature storage test is typically used to determine the effect of time and temperature, under storage conditions, for thermally activated failure mechanisms of solid state electronic devices, including nonvolatile memory devices (data retention failure mechanisms). During the test reduced temperatures (test conditions) are used without electrical stress applied. This test may be destructive, depending on Time, Temperature and Packaging (if any).

Committee(s): JC-14.1

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This test allows the user to evaluate the moisture resistance of nonhermetic packaged solid state devices. The Unbiased Autoclave Test is performed to evaluate the moisture resistance integrity of non-hermetic packaged solid state devices using moisture condensing or moisture saturated steam environments. It is a highly accelerated test that employs conditions of pressure, humidity and temperature under condensing conditions to accelerate moisture penetration through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors passing through it. This test is used to identify failure mechanisms internal to the package and is destructive.

Committee(s): JC-14.1

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This standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity.

Committee(s): JC-42.6

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This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the High Speed Unterminated Logic (HSUL_12) logic switching range, nominally 0 V to 1.2 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages.

Committee(s): JC-16

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This addendum to JESD79-3 defines the 3DS DDR3 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this specification is to define the minimum set of requirements for compliant 8Gbit through 64Gbit x4 and x8 3DS DDR3 SDRAM devices. This document was created based on the E revision of the DDR standard (JESD79). Each aspect of the changes for 3DS DDR3 SDRAM operation was considered.

Committee(s): JC-42.3

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This test standard defines the requirements and procedures for 40 to 500 MeV proton irradiation of electronic devices for Single Event Effects (SEE), and reporting the results. Protons are capable of causing SEE by both direct and indirect ionization, however, in this energy range, indirect ionization will be the dominant cause of SEE [1-3]. Indirect ionization is produced from secondary particles of proton/material nuclear reactions, where the material is Si or any other element present in the semiconductor. Direct proton ionization is thought to be a minor source of SEE, at these energies. This energy range is also selected to coincide with the commonly used proton facilities, and result in the fewest energy dependent issues during test.

Committee(s): JC-13, JC-13.4

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This document defines the LPDDR2 specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. This standard covers the following technologies: LPDDR2-S2A, LPDDR2-S2B, LPDDR2-S4A, LPDDR2-S4B, LPDDR2-N-A, and LPDDR2-N-B. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant 64 Mb through 8 Gb for x8, x16, and x32 SDRAM devices as well as 64 Mb through 32 Gb for x8, x16, and x32 for NVM devices. Item 1725.01G.

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Committee(s): JC-42.6

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Salt atmosphere is a destructive, accelerated stress that simulates the effects of severe seacoast atmosphere on all exposed surfaces. Such stressing and post-stress testing determine the resistance of solid-state devices to corrosion and may be performed on commercial and industrial product in molded or hermetic packages.

Committee(s): JC-14, JC-14.1

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This standard will be useful to users, manufacturers, educators, technical writers, and others interested in the characterization, nomenclature, and classification of microelectronics devices. There are general guidelines for both letter symbols and abbreviations applicable to all integrated circuits, and detailed sections for digital ICs, linear (analog) ICs, interface ICs (including D/A and A/D converters), voltage regulators, charge-transfer devices. The standard lists and defines more than 400 of the most common physical and electrical terms applicable to these devices and shows the industry-standard symbol and abbreviations that have been established for such terms.

Committee(s): JC-10

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