Standards & Documents Search

This standard defines the dc and ac single-ended (data) and differential (clock) operating conditions, I/O impedances, and the termination and calibration scheme for 1.8 V Pseudo Open Drain I/Os. The 1.8 V Pseudo Open Drain interface, also known as POD18, is primarily used to communicate with GDDR3 SGRAM devices.

Committee(s): JC-16

Free download. Registration or login required.

This Test Method establishes a uniform method for performing solid state device package power cycling stress test.

Committee(s): JC-14, JC-14.1

Free download. Registration or login required.

This Test Method establishes an industry standard preconditioning flow for nonhermetic solid state SMDs (surface mount devices) that is representative of a typical industry multiple solder reflow operation. These SMDs should be subjected to the appropriate preconditioning sequence of this document by the semiconductor manufacturer prior to being submitted to specific in-house reliability testing (qualification and reliability monitoring) to evaluate long term reliability (which might be impacted by solder reflow).

Committee(s): JC-14.1

Free download. Registration or login required.

This Bias Temperature Instability (BTI) stress/test procedure is proposed to provide a minimum recommendation for a simple and consistent comparison of the mean threshold voltage (Vth) BTI induced shift. The procedure enables comparison of stable and manufacturable CMOS processes and technologies in which the process variation is low and the yield is mature. Qualification and accept-reject criteria are not given in this document.

Committee(s): JC-14.2

Free download. Registration or login required.

Committee(s): JC-13

Free download. Registration or login required.

This standard establishes the requirements for timely customer notification of planned product discontinuance, which will assist customers in managing end-of-life supply, or to transition on-going requirements to alternate products.

Committee(s): JC-14, JC-14.4

This standard provides a checklist that is intended as a tool to allow users to assess the level of compliance of a quality management system to the requirements ISO 9001:2008. The questions in this checklist are of a generic nature and intended to be applicable to all organizations, not just those involved in the electronics industry. It can be useful while performing self-assessments of the organization or other internal audit procedures. It is not intended for use by a contracted third party registrar during a formal audit to the requirements of ISO 9001:2008.

Committee(s): JC-14.4

Terminology update.  

This standard establishes the requirements for an interface between Radio Front End (RF) and Baseband (BB) integrated circuits (IC).

Committee(s): JC-61

Free download. Registration or login required.

This standard establishes the preferred rating ranges and conditions for specifying beta for low power, audio frequency transistors intended for entertainment service. Formerly known as RS-302 and EIA-302.

Committee(s): JC-25

Free download. Registration or login required.

This standard applies to devices susceptible to damage by electrostatic discharge greater than 100 volts human body model (HBM) and 200 volts charged device model (CDM).

Committee(s): JC-13, JC-14.1

Free download. Registration or login required.

This test method is used to determine whether solid state devices can withstand the effect of the temperature shock to which they will be subjected during soldering of their leads in a solderwave process and/or solder fountain (rework/replacement) process. The heat is conducted through the leads into the device package from solder heat at the reverse side of the board.

Committee(s): JC-14.1

Free download. Registration or login required.

This stress method is used to determine the effects of RF bias conditions and temperature on Power Amplifier Modules (PAMs) over time. These conditions are intended to simulate the devices’ operating condition in an accelerated way, and they are expected to be applied primarily for device qualification and reliability monitoring. The purpose of this test is for use to determine the effects of nominal DC and RF bias conditions and high temperature on Power Amplifier Modules (PAMs) over time. It simulates the devices’ operating condition in an accelerated way, and is primarily intended for device qualification testing and reliability monitoring which stresses all of the modules’ thermal and electrical failure mechanisms anticipated in typical use.

Committee(s): JC-14.7

Free download. Registration or login required.

This standard defines the input, output, and termination specifications for differential signaling in the SLVS-400 environment, nominally between 0 and 400 mV. Power supplies other than the nominal 800 mV power for the SLVS interface are not specified.

Committee(s): JC-16

Free download. Registration or login required.

Semiconductor Power Control Modules (SPCM) are modules consisting of thyristors or transistors, or both, as the primary controlling elements. Methods of manufacture of semiconductor power control modules include the assembling of individual components and the use of semiconductor hybrids or monolithic processing technologies, or both.

Committee(s): JC-22.2

Free download. Registration or login required.

The purpose of these benchmarks is to provide a common set of high level functions which serve as vehicles for comparing the performance of gate arrays implemented in any technology using any internal structure. These benchmarks effectively provide an unbiased measure of gate array vendors' ability to implement a desired complex function on a particular gate array at a known level of performance.

Committee(s): JC-44

Free download. Registration or login required.

This standard is intended for use by SoC, ASIC, ASSP, and FPGA developers or vendors interested in incorporating a signaling protocol for hardware resetting the Serial Flash device. In is also intended for use by peripheral developers or vendors interested in providing Serial Flash devices compliant with the standard. This standard defines a signaling protocol that allows the host to reset the slaved Serial Flash device without a dedicated hardware reset pin. Item 1775.06.

Committee(s): JC-42.4

Free download. Registration or login required.

This standard provides a comprehensive definition of the NOR cryptographic security hardware abstraction layer (HAL). It also provides design guidelines and reference software to reduce design-in overhead and facilitate the second sourcing of secure memory devices. It does not attempt to standardize any other interaction to the NOR device that is not related to cryptographic security functionality within the device.

Committee(s): JC-42.4

Free download. Registration or login required.

This document describes a test method only; acceptance criteria and qualification requirements are not defined. This test method applies to solder ball pull force/energy testing prior to end-use attachment. Solder balls are pulled individually using mechanical jaws; force, fracture energy and failure mode data are collected and analyzed. Other specialized solder ball pull methods using a heated thermode, gang pulling of multiple solder joints, etc., are outside the scope of this document. Both low and high speed testing are covered by this document. This is a minor editorial revision to JESD22-A115A.

Committee(s): JC-14, JC-14.1

Free download. Registration or login required.

This test method provides optional conditions for preconditioning and soldering for the purpose of assessing the solderability of device package terminations. It provides procedures for dip & look solderability testing of through hole, axial and surface mount devices and a surface mount process simulation test for surface mount packages. The purpose of this test method is to provide a means of determining the solderability of device package terminations that are intended to be joined to another surface using lead (Pb) containing or Pb-free solder for the attachment.

Committee(s): JC-14.1

Terminology update, see Annex. This standard defines workloads for the endurance rating and endurance verification of SSD application classes. These workloads shall be used in conjunction with the Solid State Drive (SSD) Requirements and Endurance Test Method standard, JESD218. Also see JESD219A_MT and JESD219A_TT for the supporting trace files.

Committee(s): JC-64, JC-64.8

Free download. Registration or login required.

This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard.

Committee(s): JC-40.1

Free download. Registration or login required.

This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices.

Committee(s): JC-42.3

Free download. Registration or login required.

This standard was developed to prevent the proliferation of data transfer formats that occurred with microprocessor development systems. The focus of the standard is on field programmable devices and their support tools. It is not intended for other types of semicustom logic devices or other types of fabrication or testing equipment.

Committee(s): JC-42.1

Free download. Registration or login required.

This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (nominal) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

Free download. Registration or login required.

This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses.

Committee(s): JC-40

Free download. Registration or login required.

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a íCU877 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a íCU877 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This document includes minor editorial changes as noted in Annex A, page 16.

Committee(s): JC-40

Free download. Registration or login required.

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CUA878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

Free download. Registration or login required.

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision, shown in Annex A of the document.

Committee(s): JC-40

Free download. Registration or login required.

The purpose of this standard is to provide a standard for 2.5 V nominal supply-voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This standard defines dc interface parameters and test loading for CMOS digital logic family based on 2.5 V (nominal) power supply levels at 2.5 V input tolerance.

Committee(s): JC-40

Free download. Registration or login required.