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This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to DSBGA-packaged 1-, 2- and 3-bit logic devices.

Committee(s): JC-40

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This standard provides a pinout standard for 16-bit wide logic devices offered in a 56-ball areagrid array package to provide for uniformity, multiplicity of sources, elimination of confusion,ease of device specification, and ease of use.

Committee(s): JC-40

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This standard provides a pinout standard for 8-bit logic devices offered in a 20-ball area gridarray package to provide for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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This Test Method standardizes the test board and test methodology to provide a reproducible assessment of the drop test performance of surface mounted components.

Committee(s): JC-14, JC-14.1

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This standard defines the electrical parameters for high-speed interfaces for use in the 1.2V electrical environment. Included in the standard are a single ended signaling interface suitable for parallel buses, and a differential signaling interface suitable for clock applications or parallel differential buses. JEDEC BIC Standard JESD8-16A continues the tradition of the JESD8-xx standards, defining electrical interfaces for the industry as new technologies and bus requirements develop. Previously, JEDEC defined standard JESD8-6, the HSTL standard, for use in 1.5V electrical environments. BIC is similar to HSTL, except the power supply voltage has dropped from 1.5V to 1.2V, and interface requirements are tightened to allow much higher speeds

Committee(s): JC-16

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The intent of this standard is to be a guide in the manufacture and procurement of ceramic packages, especially for the hybrid industry. Manufacturers or ceramic packages and procuring activities for these packages will now be able to use this document as the means for agreement in the imposition of minimum requirements in qualification, screening, and quality conformance.

Committee(s): JC-13, JC-13.5

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This standard details the methods to be followed if color coding is used to identify JEDEC-assigned type numbers or for cathode identification of discrete semiconductor devices. Formerly known as EIA-236-C and/or ANSI/EIA-236-C-1986 (1995).

Committee(s): JC-10

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Terminology update.

This document should be used in conjunction with the parent document, and is intended to function as an overview to support the effective use of Compact Thermal Model (CTM) methodologies as specified in the companion methods documents.

Committee(s): JC-15, JC-15.1

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This standard defines the electrical and mechanical requirements for Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (DDR5 SDRAM CAMM2s) and Low Power Double Data Rate, Synchronous DRAM Compression-Attached Memory Modules (LP5 SDRAM CAMM2s).

Committee(s): JC-45

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This revision of JESD21 is substantially different from previous issues because it reflects advancement in semiconductor technology and computer design needs. A new class of memory devices, the multiport DRAM (MPDRAM) C also know as 'Video Ram' because of the most common application for the devices C is represented. A new family of SRAMs which addresses the increasing need for high speed is introduced. Additional families of devices in the SOJ and Zip packages are included. The material in this revision is organized primarily by function (ROM, EPROM, SRAM, DRAM, etc.) rather than by technology and word length. Pinouts for SIMM and DIMM are included along with presence detect schemes. A current set of terms has also been included. JESD21-C is a compilation of all memory device standards that have been developed by the JC-42 Committee and approved by the JEDEC BoD from September 1989 to present. This latest issue has changed to a loose-leaf format and comes in a three-ring binder so that new drawings can be added without requiring a new publication. Time of publication of the material is identified by release number, i.e., if marked Release 8, this item was approved and released in 1998, if marked Release 13, this item was approved and released in 2003.

Committee(s): JC-42

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The purpose of this test is to measure the deviation of the terminals (leads or solder balls) from coplanarity at room temperature for surface-mount semiconductor devices. This test method is applicable for inspection and device characterization. If package warpage or coplanarity is to be characterized at reflow soldering temperatures, then JESD22-B112 should be used.

Committee(s): JC-14, JC-14.1

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This standard is invoked when a supplier becomes aware that a product’s environmental compliance declaration they provided or made available to their customers had an error that might cause a customer to draw an incorrect conclusion about the compliance of the product to legal requirements.

Committee(s): JC-14.4

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This standard establishes the requirements for timely notification to affected customers after a disaster has occurred at a supplier’s facility that will affect the committed delivery of product. This standard puts specific emphasis on notification, timing, and notification content which includes risk exposure, impact analysis, and recovery plans. This standard is applicable to suppliers of, and affected customers for, solid-state products and the constituent components used within.

Committee(s): JC-14.4

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This comprehensive standard defines all required aspects of 256Mb through 4Gb DDR2 SDRAMs with x4/x8/x16 data interfaces, including pinout, addressing, functional description, features, ac and dc parametrics, truth tables, and packages. Standard JESD79-2 uses a SSTL_18 interface, which is described in another JEDEC standard called JESD8-15. The purpose of this Standard is to define the minimum set of requirements for compliant devices 256Mb through 4Gb, x4/x8/x16 DDR2 SDRAMs. System designs based on the required aspects of this specification will be supported by all DDR2 SDRAM vendors providing compliant devices. Changes between versions is indicated in Annex A. Item 1778.01

Committee(s): JC-42, JC-42.3

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This standard defines standard specifications for features and functionality, DC and AC interface parameters and test loading for definition of the DDR4 data buffer for driving DQ and DQS nets on DDR4 LRDIMM applications. Any TBDs as of this document, are under discussion by formulating committee. Item 314.11D

*If you downloaded this file between 8/7/2019 and 8/14/2019, please download again, the publication date on the document was incorrected and has been fixed.

Patents(): A complete list of Assurance/Disclosure Forms is available to JEDEC members in the Members Area. Non-members can obtain individual Assurance/Disclosure Forms on request from the JEDEC office.

Committee(s): JC-40.4

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This version is a minor editorial adding Annex B that was left out of the original publication October 2020.

An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory.  A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K.

Committee(s): JC-45.6

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This document defines the DDR4 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Standard is to define the minimum set of requirements for JEDEC compliant 2 Gb through 16 Gb for x4, x8, and x16 DDR4 SDRAM devices. This standard was created based on the DDR3 standard (JESD79-3) and some aspects of the DDR and DDR2 standards (JESD79, JESD79-2). Committee Item 1716.78H

Committee(s): JC-42.3C

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This document defines standard specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Clock Driver (CKD) for re-driving the DCK for CUDIMM, CSODIMM and CAMM applications. The DDR5CKD01 Device ID is DID = 0x0531. (5 = DDR5,
3= Clock Driver, 1= rev 01)

Committee(s): JC-40, JC-40.4

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This standard, JESD324-V0-RCA, “DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) Raw Card A Annex” defines the design detail of x8, 1 Package Ranks DDR5 CSODIMM with Clock Driver.

Committee(s): JC-45, JC-45.3

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This standard, JESD324-V0-RCC, "DDR5 Clocked Small Outline Dual Inline Memory Module (CSODIMM) RawCard C Annex" defines the design detail of x16, 1 Package Ranks DDR5 CSODIMM with Clock Driver.

Committee(s): JC-45.3

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This standard, JESD323-A0-RCA, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card A Annex” defines the design detail of x8, 1 Package Rank DDR5 NECC CUDIMM with Clock Driver.

Committee(s): JC-45, JC-45.3

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This standard, “JESD323-A0-RCC, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card C Annex” defines the design detail of x16, 1 Package Ranks DDR5 Clocked UDIMM.

Committee(s): JC-45, JC-45.3

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This annex, JESD323-A0-RCB, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card B Annex", defines the design detail of x8, 2 Package Ranks DDR5 CUDIMM. The common feature of DDR5 CUDIMM such as the connector pinout can be found in the JESD323, DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Standard.

Committee(s): JC-45, JC-45.3

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This annex, JESD323-B4-RCE, “DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Raw Card E Annex" defines the design detail of x8, 2 Package Ranks DDR5 CUDIMM. The common feature of DDR5 CUDIMM such as the connector pinout can be found in the JESD323, DDR5 Clocked Unbuffered Dual Inline Memory Module (CUDIMM) Common Standard.

Committee(s): JC-45, JC-45.3

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This standard, JESD305-R4-RCB, DDR5 Registered Dual Inline Memory Module with 4-bit ECC (EC4 RDIMM) Raw Card B Annex, defines the design detail of x4, 2 Package Ranks DDR5 RDIMM with 4-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Load Reduced (LRDIMM) and Registered Dual Inline Memory Module (RDIMM) Common Standard. Item 2273.14.

Committee(s): JC-45.1

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This standard defines the electrical and mechanical requirements for 288-position, 1.1 Volt (VDD and VDDQ), DDR5 Registered (RDIMM), Double Data Rate (DDR), Synchronous DRAM Dual In-Line Memory Modules (DIMM). These Registered DDR5 SDRAM DIMMs are intended for use in server, workstation, and database environments.

Committee(s): JC-45, JC-45.1

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This standard, JESD305-R8-RCC, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card C Annex, defines the design detail of x4, 1 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard.

Committee(s): JC-45, JC-45.1

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This standard, JESD305-R8-RCE, DDR5 Registered Dual Inline Memory Module with 8-bit ECC (EC8 RDIMM) Raw Card E Annex, defines the design detail of x8, 2 Package Rank DDR5 RDIMM with 8-bit ECC. The common feature of DDR5 RDIMM, such as the connector pinout, can be found in the JESD305, DDR5 Registered Dual Inline Memory Module (RDIMM) Common Standard.

Committee(s): JC-45, JC-45.1

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This standard defines specifications of DC interface parameters, switching parameters, and test loading for definition of the DDR5 Registering Clock Driver (RCD) with parity for driving address and control nets on DDR5 RDIMM and LRDIMM applications. The DDR5RCD02 Device ID is DID = 0x0052.

Committee(s): JC-40, JC-40.4

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