Global Standards for the Microelectronics Industry
Standards & Documents Search
Title |
Document # | Date |
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ZENER AND VOLTAGE REGULATOR DIODE RATING VERIFICATION AND CHARACTERIZATION TESTING |
JESD211.01 | Nov 2012 |
This standard is applicable to diodes that are used as voltage regulators and voltage references. It describes terms and definitions and explains methods for verifying device ratings and measuring device characteristics. Free download. Registration or login required. |
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XFM DEVICE, Version 1.0 |
JESD233 | Aug 2021 |
This standard specifies the mechanical and electrical characteristics of the XFM Device. Such characteristics include, among others, package dimensions, pin layout, signal assignment, power supply voltages, currents, and electrical characteristics of the PCIe interface. Committee(s): JC-64 Free download. Registration or login required. |
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WIRE BOND SHEAR TEST |
JESD22-B116B | May 2017 |
This fully revised test provides a means for determining the strength of gold and copper ball bonds to a die or package bonding surface, and may be performed on pre-encapsulation or post-encapsulation parts. Pictures have been added to enhance the fail mode diagrams. The wire bond shear test is destructive. The test method can also be used to shear aluminum and copper wedge bonds to a die or package bonding surface. It is appropriate for use in process development, process control and/or quality assurance. Free download. Registration or login required. |
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WIDE I/O SINGLE DATA RATE (WIDE I/O SDR) |
JESD229 | Dec 2011 |
This standard defines the Wide I/O specification, including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. This standard covers the following technologies: Wide I/O. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 1 Gb through 32 Gb SDRAM (monolithic density) devices with 4, 128b wide channels using direct chip-to-chip attach methods between 1 to 4 memory devices and a controller device. Free download. Registration or login required. |
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WIDE I/O 2 (WideIO2) |
JESD229-2 | Aug 2014 |
This standard defines Wide I/O 2 (WideIO2), including features, functionality, AC and DC characteristics, packages, and micropillar signal assignments. The purpose of this standard is to define the minimum set of requirements for JEDEC compliant, 8 Gb through 32 Gb SDRAM devices with 4 or 8 64-bit wide channels using direct chip-to-chip attach methods for between 1 and 4 memory devices and a controller/buffer device. The WideIO2 architecture is an evolution of the WIO architecture to enable bandwidth scaling with capacity. Committee(s): JC-42.6 Free download. Registration or login required. |
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