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Title	Document #	Date
DDR4 NVDIMM-P BUSS PROTOCOL	JESD304-4	Nov 2020
TEMPORARILY REMOVED 12/8/20. If your downloaded proir to this date please discard this iwill be republished shortly as JESD304-4.01An NVDIMM-P device is defined as a LRDIMM memory module which provides host controller access to DRAM and/or other memory devices such as persistent memory. A transactional protocol is described for NVDIMM-P, which may be used on a DDR interface allowing operation of both standard DRAM modules and NVDIMM-P modules on the same channel. Item 2233.98K. Committee(s): JC-45.6
UNIVERSAL FLASH STORAGE (UFS) CARD EXTENSION, Version 3.0	JESD220-2B	Nov 2020
This standard specifies the characteristics of the UFS card electrical interface and the memory device. This document defines the added/modified features in UFS card compared to embedded UFS device. For other common features JESD220, UFS, will be referenced. Patents(): Samsung: US D727910, US D736212, US D736215, US D736214, US D736213, US 29/546125, US 29/546150 Committee(s): JC-64.1 Available for purchase: $76.00 Add to Cart To help cover the costs of producing standards, JEDEC is now charging for non-member access to selected standards and design files. Most of the content on this site remains free to download with registration. Paying JEDEC member companies enjoy free access to all content. Learn more and apply today. Paying JEDEC Members may login for free access.
TEMPERATURE CYCLING	JESD22-A104F	Nov 2020
This standard provides a method for determining solid state devices capability to withstand extreme temperature cycling. This standard applies to single-, dual- and triple-chamber temperature cycling and covers component and solder interconnection testing. It should be noted that this standard does not cover or apply to thermal shock chambers. This test is conducted to determine the ability of components and solder interconnects to withstand mechanical stresses induced by alternating high- and low-temperature extremes. Permanent changes in electrical and/or physical characteristics can result from these mechanical stresses. Committee(s): JC-14.1 Free download. Registration or login required.
CYCLED TEMPERATURE HUMIDITY-BIAS WITH SURFACE CONDENSATION LIFE TEST	JESD22-A100E	Nov 2020
The Cycled Temperature-humidity-bias Life Test is performed for the purpose of evaluating the reliability of nonhermetic packaged solid state devices in humid environments. It employs conditions of temperature cycling, humidity, and bias that accelerate the penetration of moisture through the external protective material (encapsulant or seal) or along the interface between the external protective material and the metallic conductors that pass through it. The Cycled Temperature-Humidity-Bias Life Test is typically performed on cavity packages (e.g., MQUADs, lidded ceramic pin grid arrays, etc.) as an alternative to JESD22-A101 or JESD22-A110. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
DDRx SPREAD SPECTRUM CLOCKING (SSC) STANDARD	JESD404-1	Nov 2020
Definition for all DDRx component documents to reference. This is generic to any DDRxtechnology. Item 1842.34 Committee(s): JC-42.3C Free download. Registration or login required.

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