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STANDARD LIST OF VALUES TO BE USED IN SEMICONDUCTOR DEVICE SPECIFICATIONS AND REGISTRATION FORMAT:

Status: ReaffirmedMarch 2001 		JESD419-A Oct 1980

This document contains standard lists of values which are recommended for use in semiconductor device specification and JEDEC Registration Formats. Good reasons should exist in those cases where values are used that are not included in these lists. Formerly known as EIA-419-A, that superseded JEP74 (February 1996).

Committee(s): JC-25

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STANDARD FOR THE MEASUREMENT OF SMALL-SIGNAL TRANSISTOR SCATTERING PARAMETERS:

Status: ReaffirmedApril 1999, March 2009 		JESD435 Apr 1976

This standard specifies the standard for the measurement of small-signal transistor scattering parameters. Formerly known as RS-435 and/or EIA-435

Committee(s): JC-25

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STANDARD FOR THE MEASUREMENT OF CRE

Status: Reaffirmed April 1981, April 1999, March 2009 		JESD340 Nov 1967

This standard offers an easily measured parameter which is one of the significant characteristics in determining the stability of a transistor intended for small-signal operation. The measurement technique allows rapid testing. Its correlation to AC stability will help to establish the interchangeability of a device. Formerly known as RS-340 and/or EIA-340.

Committee(s): JC-25

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STANDARD FOR MEASURING FORWARD SWITCHING CHARACTERISTICS OF SEMICONDUCTOR DIODES:

Status: ReaffirmedApril 2005 		JESD286-B Feb 2000

This method updates the standard procedure for characterizing the switching of signal or switching diodes when a step function of forward current is applied. The objective is to provide a standard so that accurate comparisons can be made. Formerly known as EIA-286-A (February 1991), ANSI/EIA-286-A-1991. Became JESD286-B after revision, February 2000.

Committee(s): JC-22.4

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STANDARD FOR FAILURE ANALYSIS REPORT FORMAT:

Status: Rescinded January 2025 		JESD38 Dec 1995

This standard is to promote unification of content and format of semiconductor device failure-analysis reports so that reports from diverse laboratories may be easily read, compared, and understood by customers. Additional objectives are to ensure that reports can be easily ready by users, satisfactorily reproduced on copying machines, adequately transmitted by telefax, and conveniently stored in standard filing cabinets.

Committee(s): JC-14.4

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STANDARD FOR DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE BiCMOS LOGIC DEVICES:

 JESD55 May 1996

The purpose is to provide a standard of BiCMOS Logic series specifications for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF LOW VOLTAGE TTL-COMPATIBLE CMOS LOGIC DEVICES:

 JESD52 Nov 1995

This standard describes dc interface specifications and test environment for these devices that operate with 2.7 V to 3.6 V power supplies. The goal is to provide a consistent set of dc specifications for reference by logic suppliers and users alike.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF FAST CMOS TTL COMPATIBLE LOGIC:

 JESD18-A Jan 1993

The purpose of this standard is to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users. The standard covers specifications for description of '54/74FCTXXXX' series fast CMOS TTL compatible devices.

Committee(s): JC-40.2

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STANDARD FOR DESCRIPTION OF A 3.3 V, ZERO DELAY CLOCK DISTRIBUTION DEVICE COMPLIANT WITH THE JESD21-C PC133 REGISTERED DIMM SPECIFICATION

 JESD82-5 Jul 2002

This standard defines the PLL support devices required for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics of the PLL used on JEDEC standard modules.JESD82-5 is the latest specification to be added to the JESD82 family of specifications for memory module support devices. Additional specifications are currently under development for DDR2 support devices.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF A 3.3 V, 18-BIT, LVTTL I/O REGISTER FOR PC133 REGISTERED DIMM APPLICATIONS:

 JESD82-2 Jul 2001

This standard defines the register support devices needed for standard height and low profile registered PC133 SDRAM DIMM modules. The objective of the standard is to clearly define the functionality, pinout and electrical characteristics required for this type of SDRAM module.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF 54/74HCXXXX AND 54/74HCTXXXX HIGH SPEED CMOS DEVICES:

 JESD7-A Aug 1986

This standard provides uniformity, multiplicity of sources, eliminate confusion, and ease of device specification and design by users for HC, and HCT CMOS devices. This standard specifies electrical parameters. It also includes appendices listing part numbers.

Committee(s): JC-40.2

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STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES:

Release Number: Pt 1 		JESD20 Jan 1990

This standard describes electrical parameters for this class of CMOS devices.

Committee(s): JC-40.2

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STANDARD FOR DESCRIPTION OF 54/74ACXXXXX AND 54/74ACTXXXXX ADVANCED HIGH-SPEED CMOS DEVICES:

Release Number: Pt 2 		JESD20 Jan 1990

This standard describes electrical parameters for this class of CMOS devices.

Committee(s): JC-40.2

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STANDARD FOR DESCRIPTION OF 54/74ABTXXX AND 74BCXXX TTL-COMPATIBLE BiCMOS LOGIC DEVICES:

 JESD54 Feb 1996

The purpose is to provide a standard of BiCMOS Logic series specifications to provide for uniformity, multiplicity of sources, elimination of confusion, and ease of device specification and design by users.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF 3877 - 2.5 V, DUAL 5-BIT, 2-PORT, DDR FET SWITCH:

 JESD73-4 Nov 2001

This standard provides a set of uniform data sheet parameters for the description of a dual 5-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay.

Committee(s): JC-40, JC-40.2

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STANDARD FOR DESCRIPTION OF 3867 - 2.5 V, SINGLE 10-BIT, 2-PORT, DDR FET SWITCH:

 JESD73-3 Nov 2001

This standard provides a set of uniform data sheet parameters for the description of a single 10-bit, 2.5 V FET transmission-gate bus switch device for DDR memory module and motherboard applications. This bus switch device has a low ON resistance allowing inputs to be connected directly to outputs, with near zero propagation delay.

Committee(s): JC-40, JC-40.2

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STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES:

 JESD73-1 Aug 2001

This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this document is to provide a set of uniform data sheet parameters for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF 3.3 V NFET BUS SWITCH DEVICES WITH INTEGRATED CHARGE PUMPS:

 JESD73-2 Aug 2001

This standard covers specifications for a family of 3.3 V NMOS FET bus switch devices with integrated charge pumps. Not included in this document are device specific parameters and performance levels that the vendor must also supply for full device description. The purpose of this standard is to provide a set of uniform data sheet parameters for the description of bus switch devices. This standard includes required parameters, test conditions, test levels, and measurement methods for data sheet descriptions of bus switch devices.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES:

 JESD80 Nov 1999

The purpose of this standard is to provide a standard for 2.5 V nominal supply-voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This standard defines dc interface parameters and test loading for CMOS digital logic family based on 2.5 V (nominal) power supply levels at 2.5 V input tolerance.

Committee(s): JC-40

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STANDARD FOR DESCRIPTION OF 2.5 V CMOS LOGIC DEVICES WITH 3.6 V CMOS TOLERANT INPUTS AND OUTPUTS:

 JESD64-A Oct 2000

The purpose is to provide a standard for 2.5 V nominal supply voltage logic devices for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This specification provides for compatibility between devices operating between either the Standard Range of 1.8 V to 2.7 V or the optional Extended Range of 1.65 V to 2.7 V supply voltages, as well as over-voltage tolerance with devices operating at 3.6 V.

Committee(s): JC-40

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STANDARD FOR DEFINITION OF THE SSTV16859 2.5 V, 13-BIT TO 26-BIT SSTL_2 REGISTERED BUFFER FOR STACKED DDR DIMM APPLICATIONS:

 JESD82-4B.01 Oct 2021

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the SSTV16859 13-bit to 26-bit SSTL_2 registered buffer for stacked DDR DIMM applications. The purpose is to provide a standard for the SSTV16859 logic device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This is a minor editorial revision, shown in Annex A of the document.

Committee(s): JC-40

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STANDARD FOR DEFINITION OF THE CUA877 AND CU2A877 PLL CLOCK DRIVERS FOR REGISTERED DDR2 DIMM APPLICATIONS

 JESD82-18A Jan 2007

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of the CUA877 and CU2A877 PLL clock devices for registered DDR2 DIMM applications.The purpose is to provide a standard for the CUA877 and CU2A877 PLL clock devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD FOR DEFINITION OF CUA878 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

 JESD82-15 Nov 2005

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA878 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a CUA878 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD FOR DEFINITION OF CUA845 PLL CLOCK DRIVER FOR REGISTERED DDR2 DIMM APPLICATIONS

 JESD82-21 Jan 2007

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a CUA845 PLL clock device for registered DDR2 DIMM applications.The purpose is to provide a standard for a CUA845 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD FOR DEFINITION OF CU877 PLL CLOCK DRIVE FOR REGISTERED DDR2 DIMM APPLICATION

 JESD82-8.01 Feb 2004

This standard defines standard specifications of dc interface parameters, switching parameters, and test loading for definition of a íCU877 PLL clock device for registered DDR2 DIMM applications. The purpose is to provide a standard for a íCU877 PLL clock device, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use. This document includes minor editorial changes as noted in Annex A, page 16.

Committee(s): JC-40

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STANDARD FOR CHAIN DESCRIPTION FILE:

 JESD32 Jun 1996

This document provides a standard for describing an ISP device chain, opening up the possibility for third-party companies to provide value-added ISP software. The purpose of the Chain Description File is to describe the configuration of a programming chain made up of devices that can be connected in some serial fashion. No assumptions are made about how data is used by the device, nor about the nature or configuration of the control signals that affect programming. It will support devices configured using electrically-erasable(EE), Flash, SRAM, or any other reconfigurable cell. For devices programmed via an IEEE programmable devices in the same chain.

Committee(s): JC-42.1

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STANDARD DESCRIPTION OF LOW-VOLTAGE TTL-COMPATIBLE, 5 V TOLERANT CMOS LOGIC DEVICES:

 JESD36 Jun 1996

This standard outlines the standard dc specifications, test conditions, and test loading for logic products that are designed to tolerate input and output voltages which exceed the device's power supply. More specifically this standardizes 5 V - tolerant logic prducts that run from 'low voltage' (2.7 V to 3.6 V) power supplies. Products that meet this standard can be used to effectively interface between LVCMOS/LVTTL and 5 V TTL buses, bridging the gap between low-voltage and 5 V TTL busses.

Committee(s): JC-40

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STANDARD DESCRIPTION OF 1.5 V CMOS LOGIC DEVICES:

 JESD76-3 Aug 2001

This standard continues the voltage specification migration to the next level beyond the 1.8 V specification already established. The purpose is to provide a standard for 1.5 V nominal supply voltage CMOS logic devices, for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.1

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STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (WIDE RANGE OPERATION):

 JESD76-1 Jun 2001

This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (nominal) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD DESCRIPTION OF 1.2 V CMOS LOGIC DEVICES (NORMAL RANGE OPERATION):

 JESD76-2 Jun 2001

This standard defines dc interface, switching parameters and test loading for digital logic devices based on 1.2 V (normal range) power supply levels. The purpose is to provide a standard specification for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40

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STANDARD DATA TRANSFER FORMAT BETWEEN DATA PREPARATION SYSTEM AND PROGRAMMABLE LOGIC DEVICE PROGRAMMER:

 JESD3-C Jun 1994

This standard was developed to prevent the proliferation of data transfer formats that occurred with microprocessor development systems. The focus of the standard is on field programmable devices and their support tools. It is not intended for other types of semicustom logic devices or other types of fabrication or testing equipment.

Committee(s): JC-42.1

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SPI Safety Extensions (CRC) for Non Volatile SPI Flash Memories (QPI and xSPI)

 JESD255 Mar 2024

The JESD255 document defines CRC modes supported with 8-bit aligned and 16-bit aligned data transactions. It is limited to logical bus transactions and does not cover the electrical properties of the IO bus.

Committee(s): JC-42, JC-42.4

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SPECIALITY DDR2-1066 SDRAM

 JESD208 Nov 2007

This document defines the Specialty DDR2-1066 SDRAM specification, including features, functionalities, AC and DC characteristics, packages, and ball/signal assignments. The purpose of this Specification is to define the minimum set of requirements for JEDEC compliant 256 Mb through 4 Gb for x4, x8, and x16 Specialty DDR2-1066 SDRAM devices.

Committee(s): JC-42.3

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SPECIAL REQUIREMENTS FOR MAVERICK PRODUCT ELIMINATION AND OUTLIER MANAGEMENT

Status: Reaffirmed 		JESD50C Jan 2018

This standard applies to the identification and control of Maverick Product that can occur during fabrication, assembly, packaging, or test of any electronic component. It can be implemented for an entire product line or to segregate product that has a higher probability of adversely impacting quality or reliability.

Committee(s): JC-14, JC-14.3

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SPD5118 HUB and SERIAL PRESENCE DETECT DEVICE STANDARD

Release Number: Version 1.5.1 		JESD300-5B.01 May 2023

This standard defines the specifications of interface parameters, signaling protocols, and features for DDR5 Serial Presence Detect EEPROM with Hub function (SPD5 Hub) and integrated Temperature Sensor (TS) as used for memory module applications. The Hub feature allows isolation of a local bus from a Controller host bus. The designation SPD5118 or generic term SPD5 Hub refers to the devices specified by this standard.

Committee(s): JC-40.1

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SON/QFN PACKAGE PINOUTS STANDARDIZED FOR 1-, 2-, AND 3-BIT LOGIC FUNCTIONS

 JESD75-5 Jul 2004

This standard defines device pinout for 1-, 2- and 3-bit wide logic functions. This pinout specifically applies to the conversion of Dual-Inline-Packaged (DIP) 1-, 2- and 3-bit logic devices to SON/QFN packaged 1-, 2- and 3-bit logic devices.

The purpose of this document is to provide a pinout standard for 1-, 2- and 3-bit logic devices offered in 5-, 6- or 8-land SON/QFN packages for uniformity, multiplicity of sources, elimination of confusion, ease of device specification, and ease of use.

Committee(s): JC-40, JC-40.1

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SOLID-STATE DRIVE (SSD) ENDURANCE WORKLOADS

 JESD219A.01 Jun 2022

Terminology update, see Annex. This standard defines workloads for the endurance rating and endurance verification of SSD application classes. These workloads shall be used in conjunction with the Solid State Drive (SSD) Requirements and Endurance Test Method standard, JESD218. Also see JESD219A_MT and JESD219A_TT for the supporting trace files.

Committee(s): JC-64, JC-64.8

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SOLID STATE DRIVE (SSD) REQUIREMENTS AND ENDURANCE TEST METHOD

 JESD218B.03 Aug 2024

Terminology Update, see Annex. This standard defines JEDEC requirements for solid state drives. For each defined class of solid state drive, the standard defines the conditions of use and the corresponding endurance verification requirements. Although endurance is to be rated based upon the standard conditions of use for the class, the standard also sets out requirements for possible additional use conditions as agreed to between manufacturer and purchaser.  Revision A includes further information on SSD Capacity. Items 303.19, 303.20, 303.21, 303.22, 303.23, 303.26, 303.27, 303.28, and 303.32

Committee(s): JC-64.8

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SOLDERABILITY

Status: Rescinded 2014, this document has been replaced by J-STD-002D. 		JESD22-B102E Oct 2007

This test method provides optional conditions for preconditioning and soldering for the purpose of assessing the solderability of device package terminations. It provides procedures for dip & look solderability testing of through hole, axial and surface mount devices and a surface mount process simulation test for surface mount packages. The purpose of this test method is to provide a means of determining the solderability of device package terminations that are intended to be joined to another surface using lead (Pb) containing or Pb-free solder for the attachment.

Committee(s): JC-14.1

SOLDER BALL SHEAR

Status: Reaffirmed September 2020 		JESD22-B117B May 2014

The purpose of this test is conducted to assess the ability of solder balls to withstand mechanical shear forces that may be applied during device manufacturing, handling, test, shipment and end-use conditions. Solder ball shear is a destructive test.

Committee(s): JC-14, JC-14.1

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