Global Standards for the Microelectronics Industry
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Document # | Date |
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ADDENDUM No. 4 to JESD12 - METHOD OF SPECIFICATION OF PERFORMANCE PARAMETERS FOR CMOS SEMICUSTOM INTEGRATED CIRCUITS: |
JESD12-4 | Apr 1987 |
This standard defines how to specify various performance parameters of semicustom ICs, including cell and interconnect propagation delays, input/output levels and capacitance, and power dissipation. Committee(s): JC-44 Free download. Registration or login required. |
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ADDENDUM No. 4 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR BIPOLAR TRANSISTORS (DELTA BASE-EMITTER VOLTAGE METHOD):Status: ReaffirmedOctober 2002 |
JESD24- 4 | Nov 1990 |
The purpose of this test method is to measure the thermal impedance of the Bipolar Transistor under the specified conditions of applied voltage, current and pulse duration. The temperature sensitivity of the base-emitter voltage is used as the junction temperature indicator. This test method is used to measure the thermal response of the junction to a heating pulse. Specifically, the test may be used to measure dc thermal resistance, and to ensure proper die mountdown to its case. This is accomplished through the appropriate choice of pulse duration and heating power magnitude. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 4 to JESD8 - CENTER-TAP-TERMINATED (CTT) INTERFACE LOW-LEVEL, HIGH-SPEED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS: |
JESD8-4 | Nov 1993 |
This Addendum No. 4 to JEDEC Standard No. 8 defines the dc input and output specifications for a low-level, high-speed interface for integrated devices that can be a super-set of LVCMOS and LVTTL. Committee(s): JC-16 Free download. Registration or login required. |
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ADDENDUM No. 5 to JESD12 - DESIGN FOR TESTABILITY GUIDELINES: |
JESD12-5 | Aug 1988 |
This standard is intended to provide circuit designers with the information needed to develop complex integrated circuits that can be reliably and economically tested without compromising flexibility. Committee(s): JC-44 Free download. Registration or login required. |
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ADDENDUM No. 5 to JESD24 - SINGLE PULSE UNCLAMPED INDUCTIVE SWITCHING (UIS) AVALANCHE TEST METHOD:Status: Reaffirmedoctober 2002 |
JESD24- 5 | Aug 1990 |
This method describes a means for testing the ability of a power switching device to withstand avalanche breakdown. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 5 to JESD8 - 2.5 V 0.2 V (NORMAL RANGE), AND 1.8 V TO 2.7 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT |
JESD8-5A.01 | Sep 2007 |
This standard defines power supply voltage ranges, dc interface parameters for a high speed, low voltage family of non-terminated digital circuits driving/driven by parts of the same family. The specifications in this standard represent a minimum set of 'base line' set of interface specifications for CMOS-compatible circuits. Committee(s): JC-16 Free download. Registration or login required. |
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ADDENDUM No. 6 to JESD12 - INTERFACE STANDARD FOR SEMICUSTOM INTEGRATED CIRCUITS: |
JESD12-6 | Mar 1991 |
This standard defines logic interface levels for CMOS, TTL, ECL, and BiCC inputs and outputs. This standard is intended to provide an industry-wide set of specifications, for Application Specific Integrated Circuit (ASIC) signal inputs and outputs, both necessary and sufficient to define a circuits electrical interfacing with the external environment. JESD12-6 is intended to provide the ASIC manufacturer and user with a common set of signal interface levels. The standard defines interface levels for 5 volt operation. Committee(s): JC-44 Free download. Registration or login required. |
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ADDENDUM No. 6 to JESD24 - THERMAL IMPEDANCE MEASUREMENTS FOR INSULATED GATE BIPOLAR TRANSISTORS:Status: ReaffirmedOctober 2002 |
JESD24- 6 | Oct 1991 |
This standard describes in detail the method for thermal measurements of Insulated Gate Bipolar Transistors (IGBTs) and is suitable for use both in manufacturing and application of the devices. The method covers both thermal transient and thermal equilibrium measurements for manufacturing process control and device characterization purposes. Properly implemented, JESD24-6 provides a basis for obtaining realistic thermal parametric values that will benefit supplier's internal effectiveness and will be useful to the design and manufacturer of reliable IGBT circuits. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 6 to JESD8 - HIGH SPEED TRANSCEIVER LOGIC (HSTL)- A 1.5 V OUTPUT BUFFER SUPPLY VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS: |
JESD8-6 | Aug 1995 |
This standard is a 1.5 volt high performance CMOS-based interface document suitable for high I/O count CMOS and BiCMOS devices operating at frequencies in excess of 200 Mhz. Committee(s): JC-16 Free download. Registration or login required. |
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ADDENDUM No. 7 to JESD24 - COMMUTATING DIODE SAFE OPERATING AREA TEST PROCEDURE FOR MEASURING dv/dt DURING REVERSE RECOVERY OF POWER TRANSISTORS:Status: ReaffirmedOctober 2002 |
JESD24- 7 | Aug 1982 |
Defines methods for verifying the diode recovery stress capability of power transistors. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 7 to JESD8 - 1.8 V + -0.15 V (NORMAL RANGE), AND 1.2 V - 1.95 V (WIDE RANGE) POWER SUPPLY VOLTAGE AND INTERFACE STANDARD FOR NONTERMINATED DIGITAL INTEGRATED CIRCUIT: |
JESD8-7A | Jun 2006 |
This standard continues the voltage specification migration to the next level beyond the 2.5 V specification already established. Since this migration is driven by both process changes and performance/power, more entries can be expected in supporting required voltage levels. The rapidity of this evolution is expecting to increase because of the same feature sizes expected. Committee(s): JC-16 Free download. Registration or login required. |
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ADDENDUM No. 8 to JESD24 - METHOD FOR REPETITIVE INDUCTIVE LOAD AVALANCHE SWITCHING:Status: ReaffirmedOctober 2002 |
JESD24- 8 | Aug 1992 |
Determines the repetitive inductive avalanche switching capability of power switching transistors. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 8 to JESD8 - STUB SERIES TERMINATED LOGIC FOR 3.3 VOLTS (SSTL_3) A 3.3 V VOLTAGE BASED INTERFACE STANDARD FOR DIGITAL INTEGRATED CIRCUITS |
JESD8-8 | Aug 1996 |
This standard is a result of a major effort by the JC-16 Committee to develop a high performance CMOS-based interface suitable for high speed main memory applications in excess of 125 MHz. Committee(s): JC-16 Free download. Registration or login required. |
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ADDENDUM No. 9 to JESD24 - SHORT CIRCUIT WITHSTAND TIME TEST METHOD:Status: ReaffirmedOctober 2002 |
JESD24- 9 | Aug 1992 |
Test method to determine how long a device can survive a short circuit condition with a given drive level. Committee(s): JC-25 Free download. Registration or login required. |
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ADDENDUM No. 9B to JESD8 - STUB SERIES TERMINATED LOGIC FOR 2.5 VOLTS (SSTL_2): Includes Errata and Corrected Page 7 as of October 18, 2002. |
JESD8-9B | May 2002 |
This standard defines the input, output specifications and ac test conditions for devices that are designed to operate in the SSTL_2 logic switching range, nominally 0 V to 2.5 V. The standard may be applied to ICs operating with separate VDD and VDDQ supply voltages. This standard has been developed particularly with the objective of providing a relatively simple upgrade path from MOS push-pull interface designs. The standard is particularly intended to improve operation in situations where busses must be isolated from relatively large stubs. Committee(s): JC-16 Free download. Registration or login required. |
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ALPHA RADIATION MEASUREMENT IN ELECTRONIC MATERIALS |
JESD221 | May 2011 |
This standard applies generally to gas proportional instruments and the use thereof in measuring materials with an alpha emissivity of less than 10 a·khr-1·cm-2. The primary focus will be on materials used in semiconductor fabrication. The purpose of this document is to specify the recommended method for measuring alpha emissivity in materials utilized in the manufacturing of semiconductors. The method specifically applies to gas proportional instruments and designates recommended instrument settings. In addition, the method discusses operation of ionization counters. The document also recommends methods for determining sample size and for evaluating instrument background accurately. Free download. Registration or login required. |
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ANNUAL UPDATING SERVICE: |
JESD21-C AUS | Jan 2004 |
The JEDEC Office has generated a mailing list for those who wish to subscribe to updates of this publication. A payment is required for subscription to this updating service. Committee(s): JC-42 |
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APPLICATION SPECIFIC QUALIFICATION USING KNOWLEDGE BASED TEST METHODOLOGYStatus: Reaffirmed January 2021 |
JESD94B | Oct 2015 |
The method described in this document applies to all application specific reliability testing for solid state components with known failure mechanisms where the test duration and conditions vary based on application variables. This document does not cover reliability tests that are characterization based or essentially go / no-go type tests, for example, ESD, latch-up, or electrical over stress. Also, it does not attempt to cover every failure mechanism or test environment, but does provide a methodology that can be extended to other failure mechanisms and test environments. Committee(s): JC-14.3 Free download. Registration or login required. |
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ASSESSMENT OF AVERAGE OUTGOING QUALITY LEVELS IN PARTS PER MILLION (PPM) |
JESD16B | Nov 2017 |
This standard was revised to clarify assumptions necessary to estimate AOQ, revise the minimum sample size algorithm, address small sample size concerns, and provide methods for combining groups for AOQ estimation. Derivation of any new methods for combing groups for AOQ estimation. Derivation of any new methods introduced into this document have been provided in annexes. A statistical method is based on confidence interval statistics. A procedure was established for reporting AOQ when the minimum sample size criterion is not met. Not all sections of EIA-554 are appropriate for use by device manufacturers therefore JEDEC wishes to continue using JESD16. In December 2008 the formulating committee approved to remove EIA-554 (July 1996, Reaffirmed September 2002) from the JEDEC website. To obtain a copy of EIA-554 please contact GEIA at http://www.geia.org/ Committee(s): JC-13 Free download. Registration or login required. |
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Automotive Solid State Drive (SSD) Device StandardRelease Number: 1.1 |
JESD312 | Jan 2025 |
This standard defines the specifications of interface parameters, signaling protocols, environmental requirements, packaging, and other features for a solid state drive (SSD) targeted primarily at automotive applications. Free download. Registration or login required. |