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Title	Document #	Date
THE MEASUREMENT OF TRANSISTOR EQUIVALENT NOISE VOLTAGE AND EQUIVALENT NOISE CURRENT AT FREQUENCIES OF UP TO 20 kHz Status: Reaffirmed April 1981, April 1999, March 2009	JESD354	Apr 1968
This standard provides a method for determining values, for device registration purposes, for transistor equivalent noise voltage and equivalent noise current at frequencies up to 20 kHz. This method is applicable to transistors whose noise has a Gaussian, flat (white) or I/f power distribution. Formerly known as RS-354 and/or EIA-354 Committee(s): JC-25 Free download. Registration or login required.
THE MEASUREMENT OF SMALL-SIGNAL VHF-UHF TRANSISTOR SHORT-CIRCUIT FORWARD CURRENT TRANSFER RATIO: Status: ReaffirmedApril 1981, April 1999, March 2009	JESD371	Feb 1970
This standard describes the method to be used for the measurement of small-signal VHF-UHF transistor short-circuit forward current transfer ratio, in preparing data sheets for JEDEC registration of low power transistors. Formerly known as RS-371 and/or EIA-371. Committee(s): JC-25 Free download. Registration or login required.
THE MEASUREMENT OF SMALL-SIGNAL VHF-UHF TRANSISTOR ADMITTANCE PARAMETERS: Status: ReaffirmedApril 1981, April 1999, March 2009	JESD372	May 1970
This standard describes the method to be used for the measurement of small-signal VHF-UHF transistor admittance parameters, in preparing data sheets for JEDEC registration of low power transistors. Formerly known as RS-372 and/or EIA-372 Committee(s): JC-25 Free download. Registration or login required.
TEST TRACE FOR 64 GB - 128 GB SSD	JESD219A_TT	Jul 2012
The Test Trace file is a supporting file for implementation of the endurance verification client workload and is used in conjunction with JESD219A. This Test Trace is derived from the 128 GB Master Trace using the compression method described in JESD219 to enable testing on SSDs with a capacity range of 64 GB to 128 GB. All characteristics of this Test Trace are identical to the Master Trace except that the maximum LBA represents an SSD user capacity of 64 GB. Committee(s): JC-64.8 Free download. Registration or login required.
TEST STANDARD FOR THE MEASUREMENT OF PROTON RADIATION SINGLE EVENT EFFECTS IN ELECTRONIC DEVICES	JESD234	Oct 2013
This test standard defines the requirements and procedures for 40 to 500 MeV proton irradiation of electronic devices for Single Event Effects (SEE), and reporting the results. Protons are capable of causing SEE by both direct and indirect ionization, however, in this energy range, indirect ionization will be the dominant cause of SEE [1-3]. Indirect ionization is produced from secondary particles of proton/material nuclear reactions, where the material is Si or any other element present in the semiconductor. Direct proton ionization is thought to be a minor source of SEE, at these energies. This energy range is also selected to coincide with the commonly used proton facilities, and result in the fewest energy dependent issues during test. Committee(s): JC-13, JC-13.4 Free download. Registration or login required.
TEST PROCEDURE FOR THE MANAGEMENT OF SINGLE-EVENT EFFECTS IN SEMICONDUCTOR DEVICES FROM HEAVY ION IRRADIATION:	JESD57A	Nov 2017
This test method defines requirements and procedures for ground simulation and single event effects (SEE) and implementation of the method in testing integrated circuits. This standard is valid when using a cyclotron or Van de Graaff accelerator. Microcircuits under test must be delidded. The ions used at the facilities have an atomic number Z > 2. It does not apply to SEE testing that uses protons, neutrons, or other lighter particles. This standard is designed to eliminate any misunderstanding between users of the method and test facilities, to minimize delays, and to promote standardization of testing and test data. Committee(s): JC-13.4 Free download. Registration or login required.
TEST METHODS TO CHARACTERIZE VOIDING IN PRE-SMT BALL GRID ARRAY PACKAGES	JESD217A.01	Nov 2022
This publication provides an overview of solder void types, outlines current metrologies and test methods used for pre-SMPT solder void characterization and potential limitations, and prescribes sampling strategy for data collection, and tolerance guidelines for corrective measures. Committee(s): JC-14.1 Free download. Registration or login required.
TEST METHODS FOR THE COLLECTOR-BASE TIME CONSTANT AND FOR THE RESISTIVE PART OF THE COMMON-EMITTER INPUT IMPEDANCE Status: Reaffirmed November 1963, June 1972, April 1981, April 1999, October 2002	JESD284-A	Nov 1963
The test methods described in this Standard are generally applicable to alloy-like devices for which the usual simplified equivalent circuits can be employed. Formerly known as EIA-284-A (November 1963). Became JESD284-A when reaffirmed in October 2002. Committee(s): JC-25 Free download. Registration or login required.
TEST METHODS AND CHARACTER DESIGNATION FOR LIQUID CRYSTAL DEVICES:	JESD23	May 1982
This standard specifies a collection of procedures for testing and character designation of liquid crystal devices. Free download. Registration or login required.
TEST METHODS AND ACCEPTANCE PROCEDURES FOR THE EVALUATION OF POLYMERIC MATERIALS: Status: Reaffirmed May 2023	JESD72A	Mar 2018
This Test Method covers the minimum requirements that should be in effect for the evaluation and acceptance of polymeric materials for use in industrial, military, space, and other special-condition products which may require capabilities beyond standard commercial microelectronics applications. It is not the intent of this Publication to specify a material, but to evaluate the material to assure that the quality and reliability of the microelectronic devices are not compromised. This document replaces JEP105, JEP107 and JEP112. Committee(s): JC-13.5 Free download. Registration or login required.
Test Method for Total Ionizing Dose (TID) from X-ray Exposure in Terrestrial Applications	JESD22-B121	Nov 2023
This test method covers X-ray imaging for terrestrial applications on packaged devices. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
TEST METHOD FOR THE MEASUREMENT OF MOISTURE DIFFUSIVITY AND WATER SOLUBILITY IN ORGANIC MATERIALS USED IN ELECTRONIC DEVICES	JESD22-A120C	Jan 2022
This standard details the procedures for the measurement of characteristic bulk material properties of moisture diffusivity and water solubility in organic materials used in the packaging of electronic devices. These two material properties are important parameters for the effective reliability performance of plastic packaged surface mount devices after exposure to moisture and subjected to high temperature solder reflow. Committee(s): JC-14.1 Free download. Registration or login required.
TEST METHOD FOR REAL-TIME SOFT ERROR RATE	JESD89-1B	Jul 2021
This test is used to determine the Soft Error Rate (SER) of solid state volatile memory arrays and bistable logic elements (e.g. flip-flops) for errors which require no more than re-reading or re-writing to correct and as used in terrestrial environments. It simulates the operating condition of the device and is used for qualification, characterization, or reliability monitoring. This test is intended for execution in ambient conditions without the artificial introduction of radiation sources. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
TEST METHOD FOR ESTABLISHING X-RAY TOTAL DOSE LIMIT FOR DRAM DEVICES	JESD22-B130	Sep 2022
This test method is offered as a standardized procedure to determine the total dose limit of DRAMs by measuring its refresh time tRef degradation after the device is irradiated with an X-Ray dose. This test method is applicable to any packaged device that contains a DRAM die or any embedded DRAM structure. Some indirect test methods such as wafer level characterization of total dose induced changes in leakage of access transistors are not described in this standard but are permissible as long as a good correlation is established. Committee(s): JC-14.1 Free download. Registration or login required.
TEST METHOD FOR BEAM ACCELERATED SOFT ERROR RATE	JESD89-3B	Sep 2021
This test is used to determine the terrestrial cosmic ray Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g., flip-flops) by measuring the error rate while the device is irradiated in a neutron or proton beam of known flux. The results of this accelerated test can be used to estimate the terrestrial cosmic ray induced SER for a given terrestrial cosmic ray radiation environment. This test cannot be used to project alpha-particle induced SER. Committee(s): JC-14.1 Free download. Registration or login required.
TEST METHOD FOR ALPHA SOURCE ACCELERATED SOFT ERROR RATE	JESD89-2B	Jul 2021
This test method is offered as standardized procedure to determine the alpha particle Soft Error Rate (SER) sensitivity of solid state volatile memory arrays and bistable logic elements (e.g. flipflops) by measuring the error rate while the device is irradiated by a characterized, solid alph source. Committee(s): JC-14, JC-14.1 Free download. Registration or login required.
TEST BOARDS FOR THROUGH-HOLE PERIMETER LEADED PACKAGE THERMAL MEASUREMENTS:	JESD51-10	Jul 2000
This standard covers the design of printed circuit boards (PCBs) used in the thermal characterization of Dual-Inline Packages (DIP) and Single-Inline Packages (SIP). It is intended to be used in conjunction with the JESD51 series of standards that cover the test methods and test environments. JESD51-10 was developed to give a figure-of-merit of thermal performance that allows for accurate comparisons of packages from different suppliers. It can be used to give a first order approximation of system performance and, in conjunction with the other JESD51 PCB standards, allows for comparisons of the various package families. Committee(s): JC-15.1 Free download. Registration or login required.
TEST BOARDS FOR THROUGH-HOLE AREA ARRAY LEADED PACKAGE THERMAL MEASUREMENT:	JESD51-11	Jun 2001
This standard covers the design of printed circuit boards (PCBs) used in the thermal characterization of Pin Grid Array (PGA) packages. It is intended to be used in conjunction with the JESD51 series of standards that cover the test methods and test environments. JESD51-11 was developed to give a figure-of-merit of thermal performance that allows for accurate comparisons of packages from different suppliers. It can be used to give a first order approximation of system performance and, in conjunction with the other JESD51 PCB standards, allows for comparisons of the various package families. Committee(s): JC-15.1 Free download. Registration or login required.
TEST BOARDS FOR AREA ARRAY SURFACE MOUNT PACKAGE THERMAL MEASUREMENTS:	JESD51- 9	Jul 2000
This standard covers the design of printed circuit boards (PCBs) used in the thermal characterization of ball grid array (BGA) and land grid array (LGA) packages. It is intended to be used in conjunction with the JESD51 series of standards that cover the test methods and test environments. JESD51-9 was developed to give a figure-of-merit of thermal performance that allows for accurate comparisons of packages from different suppliers. It can be used to give a first order approximation of system performance and, in conjunction with the other JESD51 PCB standards, allows for comparisons of the various package families. Committee(s): JC-15.1 Free download. Registration or login required.
TERMS, DEFINITIONS, AND LETTER SYMBOLS FOR MICROELECTRONIC DEVICES:	JESD99C	Dec 2012
This standard will be useful to users, manufacturers, educators, technical writers, and others interested in the characterization, nomenclature, and classification of microelectronics devices. There are general guidelines for both letter symbols and abbreviations applicable to all integrated circuits, and detailed sections for digital ICs, linear (analog) ICs, interface ICs (including D/A and A/D converters), voltage regulators, charge-transfer devices. The standard lists and defines more than 400 of the most common physical and electrical terms applicable to these devices and shows the industry-standard symbol and abbreviations that have been established for such terms. Committee(s): JC-10 Free download. Registration or login required.

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JEDEC Education Series: Memory, Mobile & Modules